ICST AV9161A-01CW16, AV9161A-01CN16, ICS9161A-01CN16, ICS9161A-01CW16 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9161A

9161

Block Diagram

Dual Programmable Graphics Frequency Generator

9161-A RevG 10/04/00

The ICS9161A is a fully programmable graphics clock
generator. It can generate user-specified clock frequencies
using an externally generated input reference or a single crystal.
The output frequency is programmed by entering a 24-bit
digital word through the serial port. Two fully user­programmable phase-locked loops are offered in a single
package. One PLL is designed to drive the memory clock,
while the second drives the video clock. The outputs may be
changed on-the-fly to any desired frequency between 390 kHz
and 120 MHz. The ICS9161A is ideally suited for any design
where multiple or varying frequencies are required.

This part is ideal for graphics applications. It generates low
jitter, high speed pixel clocks. It can be used to replace multiple,
expensive high speed crystal oscillators. The flexibility of the
device allows it to generate non-standard graphics clocks.

The ICS9161A is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.

The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the phase­locked loop. The ICS9161A incorporates a patented fourth
generation PLL that offers the best jitter performance available.

• Pin-for-pin and function compatible with ICD2061A

• Dual programmable graphics clock generator

• Memory and video clocks are individually
programmable on-the-fly

• Ideal for designs where multiple or varying frequencies
are required

• Increased frequency resolution from optional pre­divide by 2 on the M counter

• Output enable feature available for tristating outputs

• Independent clock outputs range from 390 kHz to 120
MHz for VDD >4.75V

• Power-down capabilities

• Low power, high speed 0.8µ CMOS technology

• Glitch-free transitions

• Available in 16-pin, 300-mil SOIC or PDIP package

ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

EXTCLK EXTSEL

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

VCO

CMOS

OUTPUT

DRIVER

MCLK

OE

VCO

DIVIDE

(N÷)

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

VCO

REF

DIVIDE

(M÷)

MUX

CMOS

OUTPUT

DRIVER

VCLK

D14-D20

7

D0-D3

4

D11-D13

3

REF

f

D14-D20

7

D4-D10

7

D0-D3

4

D11-D13

3

24

24

MCLK

(D0-D20)

21

21

VCLK

(D0-D20)

21

21

21

REGISTERS

3

ADDRESS

INIT

ROM

POR

INIT1

INIT2

SEL0-CLK

SEL1-DATA

DECODE

LOGIC

21

DATA

CONTROL REG

XTAL
OSC

X1
X2

PD

3-TO-1

MUX

Pscale

P=2or4

REF

DIVIDE

(M÷)

D4-D10

7

VCO

DIVIDE

(N÷)

Pscale

P= 2

2

ICS9161A

Pin Descriptions

Pin Configuration

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1KLC-0LESNI

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.DNGotnwod-lluplanretnisaH

2ATAD-1LESNI

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.DNGotnwod-lluplanretni

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5DNGRWP.dnuorG

61XNI

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.latsyrceht

72XTUO.ecnaticapacdaolLATXlanretnisedulcnihcihwtuptuolatsyrC
8KLCMTUO.tuptuokcolcyromeM
9KLCVTUO.tuptuokcolcoediV

01#TUORRETUO.drowdemmargorpyllairesehtnirorrenaslangiswoltuptuO
11KLCTXENI.DDVotpu-lluplanretnisaH.tupnikcolclanretxE
210TININI .DNGotnwod-lluplanretnisaH.BSL,snoitidnocpu-rewoplaitinistceleS
31DDVRWP.rewoP
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51LESTXENI

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16-Pin 300- mil SOIC or PDIP

3

ICS9161A

Register Definitions

The register file consists of the following six registers:

Register Addressing

As seen in the VCLK Selection table, OE acts to tristate the
output. The PD# pin forces the VCLK signal high while
powering down the part. The EXTCLK pin will only be
multiplexed in when EXTSEL and SEL0 are logic 0 and SEL1
is a logic 1.

The memory clock outputs are controlled by PD# and OE
as follows:

The Clock Select pins SEL0 and SEL1 have two purposes. In
serial programming mode, these pins act as the clock and data
pins. New data bits come in on SEL1 and these bits are
clocked in by a signal on SEL0. While these pins are acquiring
new information, the VCLK signal remains unchanged. When
SEL0 and SEL1 are acting as register selects, a time-out
interval is required to determine whether the user is selecting
a new register or wants to program the part. During this initial
time-out, the VCLK signal remains at its previous frequency .
At the end of this time-out interval, a new register is selected.
A second time-out interval is required to allow the VCO to
settle to its new value. During this period of time, typically
5ms, the input reference signal is multiplexed to the VCLK
signal.

When MCLK or the active VCLK register is being re­programmed, then the reference signal is multiplexed glitch­free to the output during the first time-out interval. A second
time-Register out interval is also required to allow the VCO
to settle. During this period, the reference signal is
multiplexed to the appropriate output signal.

The ICS9161A places the three video clock registers and the
memory clock register in a known state upon power-up. The
registers are initialized based on the state of the INIT1 and
INIT0 pins at application of power to the device. The INIT pins
must ramp up with VDD if a logical 1 on either pin is required.
These input pins are internally pulled down and will default to
a logical 0 if left unconnected.

The registers are initialized as follows:

Register Initialization

Register Selection

When the ICS9161A is operating, the video clock output is
controlled with a combination of the SEL0, SEL1, PD# and
OE pins. The video clock is also multiplexed to an external
clock (EXTCLK) which can be selected with the EXTSEL
pin. The VCLK Selection Table shows how VCLK is selected.

VCLK Selection

1TINI0TINIGERM0GER1GER2GER

0
0

1
1

0
1
0
1

005.23

000.04

053.05

446.65

571.52

571.52

000.04

000.04

223.82

223.82

223.82

053.05

223.82

223.82

223.82

053.05

EO#DPLESTXE1LES0LESKLCV

0

1
1
1
1
1
1

x
0

1
1
1
1
1

x
x
x
x
0

1

x

x
x
0
0

1
1
1

x
x
0

1
0
x

1

etatsirT

hgiHdecroF
0GER
1GER

KLCTXE
2GER
2GER

EO#DPKLCM

0
1
1

x

1

0

etatsirT

GERM

NWDRWP

MCLK Selection

sserddA

)0A-2A(

retsigeRnoitinifeD

000
100
010
110
001
011

0GER
1GER
2GER

GERM

NWDRWP

GERLTNC

1retsigeRkcolCoediV
2retsigeRkcolCoediV
3retsigeRkcolCoediV

retsigeRyromeM

edomnwod-rewoProfrosiviD

retsigeRlortnoC

4

ICS9161A

Control Register Definitions

The control register allows the user to adjust various internal options. The register is defined as follows:

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125C0

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024C0

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1=4C.tuptuoKLCVehtotycneuqerfecnereferehtsexelpitlum0=4C.segnahc

scihpargehterehwsnoitacilpparoftuptuoKLCVehtotKLCMsexelpitlum

fsawolssanurtonnacrellortnoc

.FER

913C0

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delbuod,1=3C.tuo-emitlamron,0=3C.trohsootebyamlavretnituo-emiteht

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711C1

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512SN0

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.4oteulavretnuoc

411SN0

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.4oteulavretnuoc

310SN0

Pehtselacserp1=0SN.2ybretnuocNehtselacserp0=1SN.0retsigernostcA

.4oteulavretnuoc

5

ICS9161A

Serial Programming Architecture

The pins SEL0 and SEL1 perform the dual functions of select­ing registers and serial programming. In serial programming
mode, SEL0 acts as a clock pin while SEL1 acts as the data pin.
The ICS9161A-01 may not be serially programmed when in
power-down mode.

In order to program a particular register, an unlocking sequence
must occur. The unlocking sequence is detailed in the following
timing diagram:

Serial Data Register

The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).

The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK. The complement of the
data bit must be sampled on the previous falling edge of CLK.
The setup and hold time requirements must be met on both
CLK edges. For specifics on timing, see the timing diagrams
on pages 10, 11 and 12.

The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop
bit. A total of 24 bits must always be loaded into the serial data
register or an error is issued. Following the entry of the last
data bit, a stop bit or load command is issued by bringing
DATA high and toggling CLK high-to-low and low-to-high.
The unlocking mechanism then resets itself following the
load. Only after a time-out period are the SEL0 and SEL1 pins
allowed to return to a register selection function.

Since the VCLK registers are selected by the SEL0 and SEL1
pins, and since any change in their state may affect the output
frequency, new data input on the selection bits is only permitted
to pass through the decode logic after the watchdog timer has
timed out. This delay of SEL0 or SEL1 data permits a serial
program cycle to occur without affecting the current register
selection.

The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial data
register. This programming must include the start bit, shown
in Figure 1.

Following any transition of CLK or DATA, the watchdog
timer is reset and begins counting. The watchdog timer
ensures that successive rising edges of CLK and DA T A do not
violate the time-out specification of 2ms. If a time-out
occurs, the lock mechanism is reset and the data in the serial
data register is ignored.

Figure 1: Serial Data Timing