ICST AV9150F-08, ICS9150F-08 Datasheet
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9150-08
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation.
Frequency Generator & Integrated Buffers for Pentium/Pro™
9150-08 Rev E 09/28/98
Pin Configuration
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center
2.6 ns.
No external load cap for C
L
=18pF crystals
±250 ps CPU, PCI clock skew
250ps (cycle to cycle) CPU jitter
Smooth CPU frequency switching from 50 to 133 MHz
I
2
C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
56 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<5.5ns SDRAM propagation delay from Buffer Input
56-Pin SSOP
The ICS9150-08 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are selectable.
Features include three CPU, seven PCI and seventeen SDRAM
clocks. Two reference output is available equal to the crystal
frequency, plus two IOAPIC outputs powered by VDDL1.
One 48 MHz for USB is provided plus a 24 MHz. Spread
Spectrum built in at ±0.5% or ±0.25% modulation to reduce
EMI. Serial programming I
2
C interface allows changing
functions, stop clock programing and Frequency selection. It
is not recommended to use dual function I/O pins to clock
slots (ISA, PIC, CPU, DIMM). The add on card may have a
pull-up or pull-down. Additionally, the device meets the
Pentium power-up stabilization, which requires that CPU and
PCI clocks be stable within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF, 24 and 48 MHz
clock outputs typically provide better than 0.5V/ns slew rates
into 20pF.
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:18), supply for PLL core,
VDD4 = 48MHz, 24MHz
VDDL1 = IOAPIC_F
VDDL2 = CPUCLK_F (1:2)
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
ICS9150-08
Pin Descriptions
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
PIN NUMBER PIN NAME TYPE DESCRIPTION
2
REF1 OUT 14.318 MHz reference clock output
FS2
1
IN Latched frequency select input. Has pul l-up to VDD2.
3
REF0 OUT 14. 318MHz reference clock out put
PCI_STOP# IN
Halts PCICLK (0:5) at logic "0" level when low.
(in mobile, MODE=0)
4, 10, 23, 26, 34, 42,
48, 53
GND PW R Ground.
5 X1 IN 14.318MHz input. Has internal load cap, (nominal 33pF).
6 X2 OUT
Crystal output. Has internal l oad cap (33pF) and f eedback
resistor to X1
8
PCICLK_F OUT Free run ning BUS clock not afected by PCI_STOP#
MODE
1
IN
Latched input for MODE select . Converts pin 3 to PCI_STOP# when
low for power management.
9, 11, 12,
13, 14, 16
PCICLK (0:5) OUT PCI Clock Outputs.
17 BUFFERIN IN I nput for Buffers
27 SDATA IN Serial data i n for serial config port. (I
2
C)
28 SCLK IN Clo ck input for s erial config port . (I
2
C)
30
24MHz OUT 24MHz clock output for Super I/O or FD.
FS0
1
IN Latched frequency select input. Has pul l-up to VDD4.
29
48MHz OUT 48MHz clock output for USB.
FS1
1
IN Latched frequency select input. Has pul l-up to VDD2.
1, 7, 15, 20,
31, 37, 45
VDD2, VDD1,
VDD3, VDD4
PWR Nominal 3.3 V power supply, see power groups for function.
18, 19, 21, 22, 24,
25, 32, 33, 35, 36,
38, 39, 40 41, 43,
44, 46
SDRAM
(1:8) (15:12) (7:0), 16
OUT SDRAM clocks
47 C PU_ STOP # IN
Halts CPUCLK (1:2), IOAPIC0, SDRAM (0:16) clocks at logic "0"
level when low.
50, 56 VDDL2, VDDL1 PWR
CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V
nominal.
55 IOAPIC0 OUT IOAPIC clock output. (14.318 MHz) Poweredby VDDL1
51, 49 CPUCLK (1:2) OUT CPU Output clocks. Powered by VDDL2 (60 or 66. 6MHz)
52 CPUCLK_F OUT Free running CPU output clock. Not affected ty the CPU_STOP#.
54 IOAPIC_F OUT
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDL1
3
ICS9150-08
Functionality
VDD1,2,3 = 3.3V±5%, V
DDL
1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
Power Management Functionality
Mode Pin - Power Management Input Control
FS2 FS1 FS0
CPU
(MHz)
PCICLK
(MHz)
REF, IO AP IC
(M Hz)
1 1 1 100.2 33.3 (C PU/3) 14.3 18
1 1 0 133.3
1
33.3 (CPU/4)
1
14.318
101 112
1
37.3
1
14.318
1 0 0 103 34.3 (CPU/3) 14.318
0 1 1 66.8 33.4 (CPU/2) 14.318
0 1 0 83.3 41.65 (CPU/2) 14.318
0 0 1 75 37.5 (CPU/2) 14 .31 8
0 0 0 50 25 (CPU/2) 14.318
CPU_STOP# PCI_STO P#
CPUCLK
Outputs
PCICLK
(0:5)
PCICLK_F ,
REF ,
24/48MHz
and SDRAM
Crystal
OSC
VCO
0 1 Stopped Low Running Running Running Running
1 1 Running Running Running Running Running
1 0 R unning Stopped Low Running Running Runni ng
0 0 Stopped Low Stopp ed Low Running Ru nning Runni ng
MODE, Pin 8
(Latched Input)
Pin 3
0
PCI_STOP#
(INPUT)
1
Ref 0
(OUTPUT)
Note1. Performance not guaranteed
4
ICS9150-08
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknoledge bit between each byte.
B. The clock generator is a slave/receiver I
2
C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G.. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled
output state).
General I2C serial interface information
I2C is a trademark of Philips Corporation
Then Byte 0, 1, 2, etc in
sequence until STOP.
Clock Generator
Address (7 bits)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
A(6:0) & R/W#
D2
(H)
Then Byte 0, 1, 2, etc. in
sequence until STOP.
Clock Generat or
Address (7 bits)
ACK
Byte Count
Readback
ACK
A(6:0) & R/W#
D3
(H)
Bit Description PWD
Bit 7
0 - ±0.25% Spread S pectrum Mod ulation
1 - ±0.5% Spread S pectrum Mo dulation
0
Bit6 Bit5 Bit4 CPU clock PCI
Note1
Bit 6:4
111
110
100.2
133.3
2
33.3 (CPU /3)
33.3 (CPU/4)
2
101
100
112.0
2
103
37.3 (CPU/3)
2
34.3 (CPU /3)
011
010
66.8
83.3
33.4 (CPU /2)
41.65(CPU/2)
001
000
75
50
37.5 (CPU /2)
25 (CPU/2)
Bit 3
0 - Frequency is selected by hardware select, Latched
Inputs
1 - Frequency is selected by Bit 6:4 (above)
0
Bit 2
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
0
Bit 0
0 - Running
1- Tristate all outputs
0
Note1. Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1
to use Bits 6:4, then these should
be defined to desired frequency at
same write cycle.
Note2. Performance not guaranteed
Note: PWD = Power-Up Default
Loading...