ICST AV9148M-47, ICS9148M-47 Datasheet
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-47
Block Diagram
Pentium/ProTM System Clock Chip
9148-47 Rev D 08/04/98
Pin Configuration
28 pin SOIC
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, PCI, IOAPIC ,
14.314 MHz, 48 and 24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU, IOAPIC
3.3V outputs: PCI, REF
No power supply sequence requirements
28 pin SOIC
Spread Sectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
The ICS9148-47 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz,
and one selectable 48/24MHz.
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz
GNDL = CPUCLK (0:1)
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = 48MHz
VDDL = CPUCLK (0:1)
VDDL1=IOAPIC
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
ICS9148-47
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1X1IN
XTAL_IN 14.318MH z Crystal in put, has interna l 33pF load
cap and feed back resistor fro m X2
2 X2 OUT XTAL_OUT Crystal ou tput, has intern al load cap 33pF
3 GND2 PWR Ground for PCI outputs
4 PCICLK_F OUT Free Running PCI output
5, 6, 7, 8, 10 , 11 PCICLK (0:5) OUT PCI clock outp uts. TTL compati ble 3.3 V
6, 9 VDD2 PWR Power for PCICLK output s, nominally 3.3V
12 VDD3 PWR Poer for 48MHz
13 48MHz OUT Fixed CLK output @ 48MHz
14 24/48MHz OUT
Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz
if pin 27=0 a t power up.
15 GND3 PWR Ground for 48MHz
16 SEL100/66 .6# IN
Select pin for enablin g 100MHz or 66.6M Hz
H=100MHz, L= 66.6MHz (PCI always synchronou s 33.3MHz)
17 SCLK IN Clock input for I
2
C input
18 SDATA IN Data input for I
2
C input
19 GND PWR Ground for CPUCL K (0:1 )
20 VDD PWR Power for PLL core
21, 22 CPUCLK (1:0) OUT CPU and Host clock outputs nominally 2.5V
23 VDDL PWR Power for CPU outputs, nominally 2.5V
24 IOAPIC OUT IOAPIC clock output 14.318MHz.
25 VDDL PWR Power for IOAPIC
26 VDD1 PWR Power for REF outputs.
27 REF0/SEL 48# OUT/IN
14.318MHz clock outpu t/Latched input at power up. When
low, pin 14 is 48MHz.
28 GND 1 PWR Ground for REF outputs, X1, X2.
3
ICS9148-47
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
Send the address D2
(H)
.
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3
(H)
.
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
Clock Generator
Address (7 bits)
ACK
+ 8 bits
dummy
command code
ACK
+ 8 bits
dummy Byte
count
ACK
Data Byte
1
ACK
Data Byte
N
ACK
A(6:0) & R/W#
D2
(H)
Clock Generator
Address (7 bits)
ACK
Byte
Count
ACK
Data Byte
1
ACK
Data Byte
N
A(6:0) & R/W#
D3(H)
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