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AV9148F-75-T
Datasheet
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ICST AV9148F-75-T, ICS9148F-75-T Datasheet

Integrated Circuit Systems, Inc.
General Description Features
ICS9148-75
Block Diagram
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for Mother Boards
9148-75 Rev C 3/01/00
Pin Configuration
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:3)
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
The ICS9148-75 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro™, AMD™ or Cyrix™. Sixteen different reference frequency multiplying factors are externally selectable with smooth frequency transitions.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-75 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
• Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (including one free running PCICLK)
- 3AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 100MHz
- 1 REF (3.3V) @ 14.318MHz
- 1 - 48MHz (3.3V) fixed
• Skew characteristics:
- CPU – CPU
<250ps
- CPU(early) – PCI : 1-4ns
- AGP – PCI: 250ps
- PCI – PCI <500ps
• Supports Spread Spectrum modulation & I2C programming for Power Management, Frequency Select
• Efficient Power management scheme through power down PCI, AGP and CPU_STOP clocks.
• Uses external 14.318MHz crystal
• 48 pin 300mil SSOP.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
Preliminary Product Preview
2
ICS9148-75
Preliminary Product Preview
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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ICS9148-75
Preliminary Product Preview
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Power Management Functionality
Mode Pin - Power Management Input Control
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4
ICS9148-75
Preliminary Product Preview
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz
FS3 FS2 FS1 FS0
CPU, SDRAM
(MHZ) PCI (MHZ) AGP (MHZ)
REF, IOAPIC
(MHZ) 1111 105 35 7014.318 1110 110 36.6773.3414.318 1101 115 38.3376.6614.318 1100 120 40 8014.318 1011 125 41.6683.3214.318 1010 130 43.3386.6614.318 1001 135 45 9014.318 1000 140 46.6793.4414.318 0111 100 33.366.614.318 0110 95.25 31.7563.514.318 0101 83.3 33.366.614.318 0100 75 30 6014.318 0011 75 37.57514.318 0010 68.5 34.2568.514.318 0001 66.8 33.466.814.318 0000
60 30 60 14.318
5
ICS9148-75
Preliminary Product Preview
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
ACK
Byte 0
A
CK
Byte 1
A
CK
Byte 2
ACK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
ACK
Byte 6
A
CK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
6
ICS9148-75
Preliminary Product Preview
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
I2C is a trademark of Philips Corporation
Note 1: Default at power-up will be for latched logic inputs to define frequency;
Bits 2, 6:4 are default to 000
Note: PWD = Power-Up Default
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