ICST AV9148F-46, ICS9148F-46 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9148-46

Block Diagram

Pentium/ProTM System Clock Chip

9148-46 Rev E 4/20/99

Pin Configuration

28 pin SSOP

Pentium is a trademark on Intel Corporation.

 Generates system clocks for CPU, PCI, 14.314 MHz,

48 and 24MHz.
 Supports single or dual processor systems
 Skew from CPU (earlier) to PCI clock 1 to 4ns
 Separate 2.5V and 3.3V supply pins
 2.5V outputs: CPU
 3.3V outputs: PCI, REF
 No power supply sequence requirements
 28 pin SSOP
 Spread Sectrum operation optional for PLL1
 CPU frequencies to 100MHz are supported.

The ICS9148-46 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-03, and -12.

There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.

The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), five PCI (3.3V),
two REF (3.3V), one 48MHz, and one selectable 48_24MHz.

Ground Groups

GND = Ground Source Core, CPUCLK (0:1)
GND1 = REF(0:1), X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz, 24/48MHz

Power Groups

VDD = Supply for PLL core
VDD1 = REF(0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:3)
VDD3 = 48MHz, 24/48MHz
VDDL = CPUCLK (0:1)

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9148-46

Pin Descriptions

REBMUNNIPEMANNIPEPYTNOITPIRCSED

11DNGRWP.2X,1X,)1:0(FERrofdnuorG

21XNI

Fp33lanretnisah,tupnilatsyrCzHM813.41NI_LATX

2Xmorfrotsiserkcabdeefdnapacdaol
32XTUOFp33pacdaollanretnisah,tuptuolatsyrCTUO_LATX
42DNGRWPstuptuoICProfdnuorG
5F_KLCICPTUO#POTS_ICPybdetceffatoN.tuptuoICPgninnuReerF

01,9,7,6)3:0(KLCICPTUOV3.3elbitapmocLTT.stuptuokcolcICP

82DDVRWPV3.3yllanimon,stuptuoKLCICProfrewoP

113DDVRWPzHM84rofreoP
21zHM84TUOzHM84@tuptuoKLCdexiF

31zHM84_42TUO

,purewopta1=72nipfizHM42;tuptuoKLCdexiF

.purewopta0=72nipfizHM84

413DNGRWPzHM84rofdnuorG

51#6.66/001LESNI

zHM6.66rozHM001gnilbanerofniptceleS

suonorhcnyssyawlaICP(zHM6.66=L,zHM001=H

)zHM3.33

61KLCSNIIroftupnikcolC

2

tupniC

71ATADSNIIroftupniataD

2

tupniC

81#DPNI

selbasid)WOL(evitcanevirdnehwtupnisuonorhcnysA
decalperastuptuollA.ylraeOCVspots,skcolclanretni

.elcyctnerucehtfodneehttaetatsWOLani

91#POTS_UPCNI

spots)WOL(evitcanevirdnehwtupnisuonorhcnysA

.etatsWOLani)1:0(KLCUPC

02#POTS_ICPNI

spots)WOL(evitcanevirdnehwtupnisuonorhcnysA

.detceffatonsiF_KLCICP.etatsWOLani)3:0(KLCICP
12DNGRWPerocehtdna)1:0(KLCUPCrofdnuorG
22DDVRWPerocLLProfrewoP

42,32)0:1(KLCUPCTUOV5.2yllanimonstuptuokcolctsoHdnaUPC
52LDDVRWPV5.2yllanimon,stuptuoUPCrofrewoP
621FERTUOtuptuokcolcecnerefeRzHM813.41
721DDVRWP.stuptuoFERrofrewoP

82

0FERTUOtuptuokcolczHM813.41

#84LESNI.zHM84si31nip,wolnehW.purewoptatupnidehctaL

3

ICS9148-46

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controler (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 6
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Sl ave/Receiver)

Start Bit
Address

D2

(H)

AC

K

Dummy C ommand Code

AC

K

Dummy Byte Count

ACK

Byte 0

AC

K

Byte 1

AC

K

Byte 2

ACK

Byte 3

AC

K

Byte 4

AC

K

Byte 5

ACK

Byte 6

AC

K

Stop Bit

How to Write:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Coun

t

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte

4

ACK

Byte

5

ACK

Byte

6

ACK

Stop Bit

How to Read: