ICST AV9148F-37-T, ICS9148F-37-T Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9148-37

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

9148-37 Rev F 4/25/99

Pin Configuration

 Generates the following system clocks:

- 4 CPU(2.5V/3.3V) upto 100MHz.

- 6 PCI(3.3V) @ 33.3MHz

- 2AGP(3.3V) @ 2 x PCI

- 12 SDRAMs(3.3V) @ either CPU or AGP

- 2 REF (3.3V) @ 14.318MHz

 Skew characteristics:

- CPU  CPU

<250ps

- SDRAM  SDRAM

< 250ps

- CPU  SDRAM

< 250ps

- CPUAGP: < 1ns

- CPU(early)  PCI : 1-4ns  Supports Spread Spectrum modulation +0.25, ±0.6%  Serial I2C interface for Power Management, Frequency

Select, Spread Spectrum.

 Efficient Power management scheme through PCI and CPU

STOP CLOCKS.  Uses external 14.318MHz crystal  48 pin 300mil SSOP.

48-Pin SSOP

Power Groups

VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

The ICS9148-37 is the single chip clock solution for Desktop/ Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-37 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0)

ICS9148-37

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

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ICS9148-37

Functionality

VDD1, 2, 3, 4 = 3.3V±5%, V

DDL

= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C

Crystal (X1, X2) = 14.31818MHz

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CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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ICS9148-37

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controler (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

Byte 2

ACK

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9148-37

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

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