ICST AV9148F-37, ICS9148F-37 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9148-93

Advance Information

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

9148-93 Rev - 1/22/99

Pin Configuration

 Generates the following system clocks:

- 4 CPU(2.5V/3.3V) upto 100MHz.

- 6 PCI(3.3V) @ 33.3MHz

- 2AGP(3.3V) @ 2 x PCI

- 12 SDRAMs(3.3V) @ either CPU or AGP

- 2 REF (3.3V) @ 14.318MHz

 Skew characteristics:

- CPU  CPU<250ps

- SDRAM  SDRAM < 250ps

- CPU  SDRAM < 250ps

- CPU(early)  PCI : 1-4ns  Supports Spread Spectrum modulation +0.25, ±0.6%  Serial I2C interface for Power Management, Frequency

Select, Spread Spectrum.

 Efficient Power management scheme through PCI and CPU

STOP CLOCKS.  Uses external 14.318MHz crystal  48 pin 300mil SSOP.

48-Pin SSOP

Power Groups

VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

The ICS9148-93 is the single chip clock solution for Desktop/ Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-93 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0).

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

ICS9148-93

Advance Information

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

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ICS9148-93

Advance Information

Functionality

VDD1, 2, 3, 4 = 3.3V±5%, V

DDL

= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C

Crystal (X1, X2) = 14.31818MHz

5.2_#3.3UPC

leveltupnI

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rofdetceleSreffuB

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1DDVV5.2

0DDVV3.3

CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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100 00.5700.0300.06 101 13.3823.3346.66 110 52.5957.1305.36 111 00.00133.3366.66

ICS9148-93

Advance Information

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

General I

C serial interface information

The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.

How to Write:

 Send the address D2

(H)

 Send two additional dummy bytes, a command code

and byte count.

 Send the desired number of data bytes.

See the diagram below:

Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must be sent.

How to Read:

 Send the address D3

(H)

 Send the byte count in binary coded decimal  Read back the desired number of data bytes

See the diagram below:

The following specifications should be observed:

1. Operating voltage for I2C pins is 3.3V

2. Maximum data transfer rate (SCLK) is 100K bits/sec.

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I2C is a trademark of Philips Corporation

Note 1. Default at Power-up will be for latched logic inputs,

as defined by Bit 3.

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ICS9148-93

Advance Information

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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6tiB71 )tcanI/tcA(F_KLCICP

5tiB511 )tcanI/tcA(0PGA

4tiB311 )tcanI/tcA(4KLCICP

3tiB211 )tcanI/tcA(3KLCICP

2tiB111 )tcanI/tcA(2KLCICP

1tiB011 )tcanI/tcA(1KLCICP

0tiB81 )tcanI/tcA(0KLCICP

tiB#niPDWPnoitpircseD

7tiB821 )tcanI/tcA(7MARDS 6tiB921 )tcanI/tcA(6MARDS 5tiB131 )tcanI/tcA(5MARDS 4tiB231 )tcanI/tcA(4MARDS 3tiB431 )tcanI/tcA(3MARDS 2tiB531 )tcanI/tcA(2MARDS

1tiB731 )tcanI/tcA(1MARDS

0tiB831 )tcanI/tcA(0MARDS

Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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2tiB811

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