ICST AV9148F-32, ICS9148F-32 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9148-32

Block Diagram

Pentium/ProTM System Clock Chip

9148-32 Rev B 09/09/98

Pin Configuration

48-Pin SSOP

Pentium is a trademark on Intel Corporation.

 Generates system clocks for CPU, IOAPIC, PCI,

14.314 MHz REF , USB, and Super I/O  Supports single or dual processor systems I2C interface  Supports Spread Spectrum modulation for CPU & PCI

clocks, ±0.255% Center Spread or 0 to -0.6% Down

Spread.  Skew from CPU (earlier) to PCI clock 1 to 4ns  CPU cycle to cycle jitter ±200ps  2.5V or 3.3V output: CPU, IOAPIC  3.3V outputs: PCI, REF, 48MHz  No power supply sequence requirements  Uses external 14.318MHz crystal, no external load cap

required for CL=18pF crystal  48 pin 300 mil SSOP

The ICS9148-32 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing.

Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up.

PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks.

Serial I2C interface allows power management by output clock disabling.

High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.

The ICS9148-32 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.

Power Groups

VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz, 24/48MHz# VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3)

Ground Groups

GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 = PCICLK_F, PCICLK (0:6) GND3 = 48MHz, 24/48MHz# GNDL1 = IOAPIC (0:1) GNDL2 = CPUCLK (0:3)

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9148-32

Pin Descriptions

Select Functions

Functionality CPU

PCI,

PCI_F

REF IOAPIC

48 MHz

Selection

Tristate HI - Z HI - Z HI - Z HI - Z HI - Z

Testmode T CLK/2

TCLK/6

TCLK

TCLK/2

Spread Spectrum Modulated2Modulated214.318MHz 14.318MHz 48.0MHz

PIN NUMBER PIN NAME TYPE DESCRIPTION

1 REF0/SEL48# OUT/IN

14.318MHz clock output / Latched input at power up. When low, pin 23 is 48MHz.

2, 47 REF (1:2) OUT 14.318MHz clock output

3 GND1 PWR Ground for REF outputs 4X1IN

XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2

5 X2 OUT XTAL_OUT Crystal output, has internal load cap 33pF

6, 12, 18 GND2 PWR Ground for PCI outputs

7 PCICLK_F OUT Free Running PCI output

8, 10, 11, 13, 14, 16, 17 PCICLK (0:6) OUT PCI clock outputs. TTL compatible 3.3V

9, 15 VDD2 PWR Power for PCICLK outpu ts, nominally 3.3V 19, 33 VDD PWR Isolated power for core, nominally 3.3V 20, 32 GND PWR Isolated ground for core

21 VDD3 PWR Power for 48MH z outputs, nominally 3. 3V 22 48MHz OUT 48MHz output

23 24/48MHz# OUT

Fixed clock ou tput. 24MHz if pin1=1 at power up 48MHz if pin 1=0 at power up

24 GND3 PWR Ground for 48MHz o utputs 25 SEL100/66.6# IN

Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66. 6MHz (PCI always syn chronous 33.3MHz )

26 SCLK IN Clock input for I

C input

27 SDATA IN Data input for I

C input

SPREAD# IN Enables Spread Spectrum feature when LOW

PD# IN Powers down chip, active low

CPU_STOP# IN Halts CPU clocks at lo gic "0" level when low

PCI_STOP# IN Halts PCI Bus at logic "0" level when low 37, 41 VDDL2 PWR Power for CPU outputs, nomina lly 2.5V 34, 38 GNDL2 PWR Groun d for CPU outputs.

35, 36, 39, 40 CPUCLK (3:0) OUT CPU and Host clock outputs, nominally 2.5V

42 N/C - Not internally connected 43 GNDL1 PWR Ground for IOAPIC out puts

44, 45 IOAPIC (0:1) OUT IOA PIC outputs (14.31 8MHz) nominal ly 2.5V

46 VDDL1 PWR Power for IO APIC outputs, nominally 2.5V

ICS9148-32

T echnical Pin Function Descriptions

VDD, VDD (1,2,3)

This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1.

This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet.

VDDL (1,2)

This is the power supply for the CPUCLK (0:3) and IOAPIC output buffers. The voltage level for these outputs may be

2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet.

GND, GND (1,2,3)

This is the ground to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz 0, 48MHz1.

GNDL (1,2)

This is the ground for the CPUCLK (0:3) and IOAPIC output buffers.

This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. With a nominal value of 33pF no external load cap is needed for a CL=17 to 18pF crystal.

This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor nominally 33pF.

CPUCLK (0:3)

These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them.

48MHz

This is a fixed frequency Clock output that is typically used to drive USB devices.

24/48MHz

Fixed frequency clock output. 24MHz output if Pin1=1 at power up. 48MHz if pin1=0 at power up.

IOAPIC (0:1)

This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or

3.3volts.

REF0/SEL 48#

This is an input pin during power up only. During power up if high, then pin 23 is a 24MHz fixed clock during normal operation. If Low during power up, pin 23 is a 48MHz fixed clock during normal operation. During normal operation, REF0 is an output which is a fixed frequency running at 14.318MHz.

REF(1:2)

The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:6) and is FREE RUNNING, and will not be stopped by PCI_STOP#.

PCICLK (0:6)

These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 33.3 MHz.

SEL 100/66.6#

This Input pin controls the frequency of the Clocks at the CPUCLK, PCICLK and SDRAM output pins. If a logic 1 value is present on this pin, the 100MHz Clock will be selected. If a logic 0 is used, the 66.6MHz frequency will be selected. The PCI clock is multiplexed to be 33.3MHz for both select cases. PCI is synchronous at the rising edge of PCI to the CPU rising edge (with the skew making CPU early).

ICS9148-32

T echnical Pin Function Descriptions

PWR_DWN#

This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms.

CPU_STOP#

This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. This input pin is valid only when MODE=0 (Power Management Mode)

PCI_STOP#

This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not affect PCICLK_F nor any other outputs. This input pin is valid only when MODE=0 (Power Management Mode)

ICS9148-32

Power Management

ICS9148-32 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independent of these.

SIGNAL SIGNAL STATE

Latency

No. of rising edges of free

running PCICLK

CPU_ STOP# 0 (Disabled)

1 (Enabled)

PCI_STOP# 0 (Disabled)

1 (Enabled)

PD# 1 (N ormal Op eration )

3ms

0 (Power Down)

2max

CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK PC ICLK

Other Clocks,

REF,

IOAPICs, 48 MHz 0 48 MHz 1

Crystal VCOs

X X 0 L ow Low Stopped Off Off

0 0 1 Low Low Running Running Running 0 1 1 Low 33.3 MHz Running Runn ing Running 1 0 1 100/66.6MHz L ow Running Ru nning Running 1 1 1 100/66.6MHz 33.3 MHz Run ning Running Runni ng

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