ICST AV9148F-25, ICS9148F-25 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9148-25

Block Diagram

Pentium/ProTM System and Cyrix™ Clock Chip

9148-25 Rev B 5/20/99

Pin Configuration

48-Pin SSOP

Pentium is a trademark on Intel Corporation.

• Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.318 MHz ), USB, Plus Super I/O

• Spread spectrum for CPU/SDRAM/PCI clocks default

• Supports single or dual processor systems

• Modulation of Spread Spectrum selectable as ±0.5, ±1.0, ±2.0 or none

• Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3 and 68MHz (Turbo of 66.6) speeds.

• Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on PCI clocks

• CPU clocks to PCI clocks skew 1-4ns (CPU early)

• MODE input pin selects optional power management input control pins

• T wo fixed outputs, 48MHz and 24 MHz

• Separate 2.5V and 3.3V supply pins

- 2.5V or 3.3V output: CPU, IOAPIC (Strength

selectable)

- 3.3V outputs: SDRAM, PCI, REF , 48/24 MHz

• No power supply sequence requirements

• 48 pin 300 mil SSOP

The ICS9148-25 is a Clock Synthesizer chip for Pentium and PentiumPro plus Cyrix CPU based Desktop/Notebook systems that will provide all necessary clock timing.

Features include four CPU, seven PCI and eight SDRAM clocks. T wo reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up.

High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50 ±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.

The ICS9148-25 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V supply.

Sperad Spectrum is modulated in center-spread mode on CPU/ SDRAM/PCI clocks. Modulation amount is selectable at power-up (latched inputs) for ±0.5, ±1.0, ±2.0 or No spreading.

Power Groups

VDD = Supply for PLL core. VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F , PCICLK (0:5) VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP# VDD4 = 48MHz, 24MHz VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3)

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9148-25

Pin Descriptions

Functionality

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VDD = 3.3V ±5% V

DDL

= 2.5V ±5% or 3.3V ±5%, TA = 0 to 70°C

Crystal (X1, X2) = 14.31818 MHz

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Mode Pin - Power Management Input Control

Power Management Functionality

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Spread Spectrum Functionality

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ICS9148-25

T echnical Pin Function Descriptions

VDD(1,2,3,4)

This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B and SDRAM(0:7).

This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet.

VDDL1,2

This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be

2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. See control pin CPUCLK3.3_2.5# for output buffer strength matching VDDL required for skew control.

GND

This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers.

This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. Also includes feedback resistor from X2.

This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor.

CPUCLK (0:3)

These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. See control pin CPUCLK3.3_2.5# for output buffer strength matching VDDL required for CPU to SDRAM skew control. These clocks are modulated by Sperad Spectrum.

SDRAM(0:7)

These Output Clocks are use to drive Dynamic RAM’s and are low skew copies of the CPU Clocks. The voltage swing of the SDRAM’s output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. These clocks are modulated by Sperad Spectrum.

48MHz

This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices.

24MHz

This pin is a fixed frequency clock output typically used to drive Super I/O devices.

IOAPIC

This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or

3.3volts.

REF(0:2)

The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:5) and is FREE RUNNING, and will not be stopped by PCI_STP#. This clock is modulated by Spread Spectrum.

PCICLK (0:5)

These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency , or CPU/2.5, see frequency table. These clocks are modulated by Sperad Spectrum.

FS (0,1,2)

These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. See frequency table. These pins are all Full-time inputs with a pull-up to VDD.

MODE

This Input pin is used to select the Input function of the Power Management I/O pins 26 and 27. An active Low will place pins in the Input mode and enable those stop clock functions. This pin is a full-time input with a pull-up to VDD.

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