ICST AV9148F-17-T, ICS9148F-17-T Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9148-17

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

9148-17 Rev G 4/27/00

Pin Configuration

 3.3V outputs: SDRAM, AGP, PCI, REF, 48/24 MHz  2.5V or 3.3V outputs: CPU  20 ohm CPU clock output impedance  20 ohm PCI clock output impedance  CPU to PCI skew = 2 to 6ns  No external load cap for C

=18pF crystals  250 ps max CPU, PCI clock skew  Smooth CPU frequency transition among all CPU

frequencies. I2C interface for programming  2ms power up clock stable time  Clock duty cycle 45-55%.  48 pin 300 mil SSOP package  3.3V operation, 5V tolerant inputs.

48-Pin SSOP

Power Groups

VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

The ICS9148-17 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions.

Features include four CPU, six PCI, two AGP (=2xPCI) and Twelve SDRAM clocks. Two reference outputs are available equal to the crystal frequency. One 48 MHz for USB, and one 24 MHz clock for Super IO. Built in ±1.5%, 0.6% center or down spread spectrum modulation to reduce EMI. Serial programming I2C interface allows changing functions, stop clock programing and frequency selection. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up.

High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates.

CPU_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

24MHz

REF (0:1)

CPUCLK (0:3)

SDRAM (0:11)

PCICLK (0:4)

PCICLK_F

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

SDATA

SCLK

FS(0:2)

MODE

CPU3.3#_2.5

Control

Logic

Config.

Reg.

AGP(0:1)

LATCH

POR

PCI_STOP

CPU_STOP

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9148-17

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

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ICS9148-17

Functionality

VDD1, 2, 3, 4 = 3.3V±5%, V

DDL

= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C

Crystal (X1, X2) = 14.31818MHz

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1DDVV5.2

0DDVV3.3

CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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11 gninnuRgninnuRgninnuRgninnuRgninnuR

10 gninnuRwoLdeppotSgninnuRgninnuRgninnuR

2SF1SF0SF

MARDS,UPC

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ICP

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PGA

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011 575.7357813.41 010 5.8652.435.86813.41 001 8.664.338.66813.41 000 060306813.41

ICS9148-17

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

ACK

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9148-17

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

I2C is a trademark of Philips Corporation

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111 011 101 001 110 010 100 000

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2.001

3.38 57 57

5.86

8.66 06

ICP

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5.73

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PGA

8.66 06 46 46 57

5.86

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1tiB

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gninnuR-0

stuptuollaetatsirT-1

Note 1. Default at Power-up will be for latched logic inputs

to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use bits 6:4, then these should be defined to desired frequency at same write cycle.

Note: PWD = Power-Up Default

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