ICST AV9148F-12, AV9148G-12, ICS9148F-12, ICS9148G-12 Datasheet
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-12
Block Diagram
Pentium/ProTM System Clock Chip
9148-12 Rev F 4/1/99
Pentium is a trademark on Intel Corporation.
CPU outputs are stronger drive for multiple loads per pin
(ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O
Supports single or dual processor systems
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Two fixed outputs separately selectable as 24 or 48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP and 240 mil TSSOP
Output enable register
for serial port control: 1 = enable
0 = disable
The ICS9148-12 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available equal to
the crystal frequency. Stronger drive CPUCLK outputs
typically provide greater than 1 V/ns slew rate into 20pF
loads. This device meets rise and fall requirements with 2
loads per CPU output (ie, one clock to CPU and NB chipset,
one clock to two L2 cache inputs).
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP#
will stop PCICLK (0:5) clocks. CPU and IOAPIC output
buffer strength controlled by CPU 3.3_2.5# pin to match
VDDL voltage.
PCICLK outputs typically provide better than 1V/ns slew rate
into 30pF loads while maintaining 50±5% duty cycle. The REF
clock outputs typically provide better than 0.5V/ns slew rates.
The ICS9148-12 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C
Crystal (X1, X2) = 14.31818 MHz
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Pin Configuration
48-Pin SSOP & TSSOP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
ICS9148-12
Pin Descriptions
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
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3
ICS9148-12
Power-On Conditions
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced
are on the MODE pin as shown in the table below.
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4
ICS9148-12
T echnical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from Ground
to this level. For the actual guaranteed high and low voltage
levels for the Clocks, please consult the DC parameter table
in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies
will have a voltage swing from Ground to this level. For the
actual Guaranteed high and low voltage levels of these
Clocks, please consult the DC parameter table in this Data
Sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. See the data tables for the value of this
capacitor.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor that is connected to ground. See the Data
Sheet for the value of this capacitor.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which
are in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks are controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing
of the SDRAMs output is controlled by the supply voltage
that is applied to VDD3 of the device, operates at 3.3 volts.
48/24MHzA, B
This is a fixed frequency Clock output that is typically used
to drive Super I/O devices. Outputs A and B are defined as
24 or 48MHz by I2C register (see table).
IOAPIC
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level
swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
REF(0:1)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and
X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING,
and will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the
current PCI specification. They run at 1/2 CPU frequency.
SELECT 66.6/60MHz#
This Input pin controls the frequency of the Clocks at the
CPU, PCICLK and SDRAM output pins. If a logic 1 value
is present on this pin, the 66.6 MHz Clock will be selected.
If a logic 0 is used, the 60MHz frequency will be selected.
MODE
This Input pin is used to select the Input function of the I/
O pins. An active Low will place the I/O pins in the Input
mode and enable those stop clock functions.
5
ICS9148-12
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic 0 (ground) will indicate
2.5V operation and a logic 1 will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I2C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
T echnical Pin Function Descriptions
6
ICS9148-12
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
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