ICST AV9148F-111, ICS9148F-111 Datasheet

Integrated Circuit Systems, Inc.

ICS9148-111

Third party brands and names are the property of their respective owners.

Block Diagram

9148-111 Rev A 10/19/99

Functionality

Pin Configuration

48-Pin 300mil SSOP

Recommended Application:

ALI (Aladdin V



) mobile.

Output Features:

• 3 - CPUs @ 2.5V/3.3V, up to 100MHz.

• 3 - AGPCLK @ 3.3V

• 13 - SDRAM @ 3.3V, up to 100MHz.

• 6 - PCI @ 3.3V, including one free running.

• 1 - 48MHz, @ 3.3V fixed.

• 1 - REF @ 3.3V, 14.318MHz.

Features:

• Up to 100MHz frequency support

• Support power management: CPU, PCI, AGP stop and, Power down Mode from I

C programming.

• Spread spectrum for EMI control (0 to -0.6%, ± 0.25%).

• Uses external 14.318MHz crystal

• FS pins for frequency select

Key Specifications:

• CPU – CPU: <250ps

• SDRAM - SDRAM: <250ps

• AGP-AGP: <250ps

• PCI – PCI: <500ps

• CPU-SDRAM <500ps

• CPU(early)-PCI: 1-4ns, Center 2-6ns

• CPU-AGP <500ps

Frequency Generator & Integrated Buffers for PENTIUM/Pro

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

1 1 1 100 33.33 66.67 14.318 1 1 0 95.25 31.75 63.50 14.318 1 0 1 83.3 33.30 66.60 14.318 1 0 0 75 30.00 60.00 14.318 0 1 1 91.5 30.50 61.00 14.318 0 1 0 96.22 32.07 64.15 14.318 0 0 1 66.8 33.40 66.80 14.318 0 0 0 60 30.00 60.00 14.318

PCI

(MHz)

REF,

IOAPIC

(MHz)

FS2 FS1 FS0

CPU,

SDRAM

(MHz)

AGP

(MHz)

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9148-111

Third party brands and names are the property of their respective owners.

Pin Configuration

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

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ICS9148-111

Third party brands and names are the property of their respective owners.

General Description Power Groups

VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:12), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:2)

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CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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The ICS9148-111 is a single chip clock solution for Desktop/ Notebook designs using the ALI (Aladdin V



) mobile style chipset. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-111 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.

ICS9148-111

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.

 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

ACK

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9148-111

Third party brands and names are the property of their respective owners.

Bit PWD

Bit6 Bit5 Bit4 CPU Clock PCI AGP

111

100 33.33 66.67

110

95.25 31.75 63.50

101

83.3 33.30 66.60

100

75 30.00 60.00

011

91.5 30.50 61.00

010

96.22 32.07 64.15

001

66.8 33.40 66.80

000

60 30.00 60.00

Description Must be 0 for normal operation 0 - - +/ - 0.25% Spread S p e ctrum Modulation 1 -- +/- 0.6% Spread Spectrum Modulation

Bit 7

Bit 3

Bit 2

Note 1Bit 6:4

0 - R unning

0 - Fre quency is selected by har dware select, Latched i np uts 1 - Fre quency is selected by Bit 6:4 (above) Must be 0 for normal operation 0 - Spre ad S pe c t rum ce nte r spread type.

Bit 1

Bit 0

1 - T ristate all out

uts

1 - Spre ad Spec t rum down spread type. 0 - Normal 1 - Spread Spectrum Enabled

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if

bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.

Note: PWD = Power-Up Default

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

ICS9148-111

Third party brands and names are the property of their respective owners.

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

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Byte 6: Optional Register for Possible Furture Requirements

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for future applications.

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