ICST AV9148F-11, ICS9148F-11 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9148-11

Block Diagram

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM

TM

9148-11 RevB 12/09/97P

Pin Configuration

The ICS9148-11 generates all clocks required for high speed RISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.

High drive BCLK outputs typically provide greater than 1 V/ns slew
rate into 30 pF loads. PCLK outputs typically provide better than 1V/
ns slew rate into 20 pF loads while maintaining

50±

5% duty cycle.
The REF clock outputs typically provide better than 0.5V/ns slew
rates.

 Generates four processor, six bus, one 14.31818MHz and 12

SDRAM clocks.

 Synchronous clocks skew matched to 250ps window on

CPU, SDRAM and 500ps window on BUS clocks.
 CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
 Test clock mode eases system design
 Custom configurations available
 VDD(1:3) - 3.3V ±10%

(inputs 5V tolerant w/series R )
 VDDL(1:2) - 2.5V or 3.3V ±5%
 PC serial configuration interface
 Power Management Control Input pins
 48-pin SSOP package

48-Pin SSOP

Functionality

OE

CPUCLK,

SDRAM

(MHz)

X1, REF

(MHz)

PCICLK

(MHz)

0 High-Z High-Z High-Z
1 66.6 14.318 33.3

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

2

ICS9148-11

Pin Descriptions

Power Groups

VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,
SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)

PIN NUMBER PIN NAME TYPE DESCRIPTION

2 REF0 OUT 14.318 MHz reference clock output s.

3, 9, 16, 22, 27,

33, 39, 45

GND PWR Ground.

4X1 IN

XTAL_IN 14.318MHz Crystal input , has internal 33pF load cap and f eed
back resistor from X2

5 X2 OUT

XTAL_OUT Crystal output, has internal load cap 33pF

25 MODE IN Mode select pin for enabling power manag ement features.

7 PCLK_F OUT Fr ee running BUS clock dur ing PCI_STOP# = 0.

8, 10, 11, 12

13, 15

PCICLK (0:5) OUT BUS clock outputs.

26 OE IN

Logic input for output enable, tristates all outputs when low.

23 SDATA IN Serial data in for serial config port.
24 SCLK IN Clock i nput for serial co nfig port.

1, 6, 14,

19, 30, 36,

VDD1, VDD2,
VDD3

PWR Nominal 3.3V power sup ply, see power groups for f unction.

17, 18, 20, 21,

32, 34, 35, 37, 38

SDRAM
(0:4) (8:11)

OUT SDR AM clocks 66.6MHz.

42, 48 VDDL2, VDDL1 PWR

CPU and IOAPIC cl ock power supply, either

2.5 or 3.3V nomi nal

40, 41, 43, 44 CPUCLK (0:3) O UT CPU output cl ocks, powered by VDDL 2 (66.6 MHz)

46, 47 IOAPIC (0:1) OUT IOAPIC clock output, ( 14.318 MHz) powered b y VDDL1

28

SDRAM7 OUT SDRAM clock 66.6 MHz selected
PCI_STOP# IN Halts PCICLK (0:5) at logic "0" level when low

29

SDRAM6 OUT SDRAM clock 66.6 MHz selected
CPU_STOP# IN Halts CPUCLK clocks at logic "0" level when low

31

SDRAM5 OUT SDRAM clock 66.6 MHz selected
PWR_DWN# IN Powers down chip, active low

3

ICS9148-11

Power-On Conditions

Example:
a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.
b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.

Power-On Default Conditions

At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.

CLOCK DEFAULT CONDITION AT POWER-UP

REF 0 14.31818 MHz

IOAPIC (0:1) 14.31818 MHz

MODE P IN # DES CRIPTION FUNCTION

1

44, 43, 41, 40 CPUCLKs 66.6 MHz - w/serial config enable/disable

38, 37, 35, 34,
32, 31, 21, 20,

18, 17, 29, 28

SDRAM 66.6 MHz - All SDRAM outputs

8, 10, 11,

12, 14, 15, 7

PCICLKs 33.3 MHz - w/serial config enable/disable

0

28 PCI_STOP#

Power Management, PCI (0:5) Clocks Stopped
when low

29 CPU_STOP#

Power Management, CPU (0:3) Clocks Stopped
when low

31

SDRAM/PWR

_DWN#

Used as PWR_DWN# when lo w

7 PCICLK_F

33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management

44, 43, 41, 40 CPUCLKs

66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.

38, 37, 35,
34, 32, 21,

20, 18, 17

SDRAM

66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.

8, 10, 11,

12, 14, 15

PCICLKs

33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.

4

ICS9148-11

VDD(1,2,3)

This is the power supply to the internal core logic of the device as well
as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B
and SDRAM(0:7).

This pin operates at 3.3V volts. Clocks from the listed buffers that it
supplies will have a voltage swing from Ground to this level. For the
actual guaranteed high and low voltage levels for the Clocks, please
consult the DC parameter table in this data sheet.

VDDL1,2

This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers that each supplies will have a voltage swing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.

GND

This is the power supply ground (common or negative) return pin for
the internal core logic and all the output buffers.

X1

This input pin serves one of two functions. When the device is used
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. This pin also implements an internal Crystal loading capacitor
that is connected to ground. With a nominal value fo 33pF no
external load cap is needed for a C

L

=17 to 18pF crystal.

X2

This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
output signal that drives (or excites) the discrete Crystal. The X2 pin
will also implement an internal Crystal loading capacitor nominally
33pF.

CPUCLK (0:3)

These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
Clocks are controlled by the Voltage level applied to the VDDL2 pin
of the device. See the Functionality Table for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.

SDRAM(0:11)

These Output Clocks are use to drive Dynamic RAMs and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAMs output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.

IOAPIC (0:1)

This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.

Technical Pin Function Descriptions

REF0

The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically

14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.

PCICLK (0:5)

These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification. They run at 1/2 CPU frequency.

MODE

This Input pin is used to select the Input function of the I/O pins. An
active Low will place the I/O pins in the Input mode and enable those
stop clock functions.

PWR_DWN#

This is an asynchronous active Low Input pin used to Power Down
the device into a Low Power state by not removing the power supply.
The internal Clocks are disabled and the VCO and Crystal are
stopped. Powered Down will also place all the Outputs in a low state
at the end of their current cycle. The latency of Power Down will not
be greater than 3ms. The I

2

C inputs will be Tri-Stated and the device
will retain all programming information. This input pin only valid when
MODE=0 (Power Management Mode)

CPU_STOP#

This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks including
SDRAM clocks will continue to run while this function is enabled.
The CPUCLKs will have a turn ON latency of at least 3 CPU
clocks. This input pin only valid when MODE=0 (Power Management
Mode)

PCI_STOP#

This is a synchronous active Low Input pin used to stop the PCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
Management Mode)

I

2

C

The SDATA and SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I

2

C protocol.
It will allow read-back of the registers. See configuration map for
register functions. The I

2

C specification in Philips I2C Peripherals

Data Handbook (1996) should be followed.

OE

Output Enable tristates the outputs when held low. This pin will
override the I

2

C Byte 0 function, so that the outputs will be tristated

when the OE is low regardless of the I

2

C defined function. When OE

is high, the I

2

C function is in active control.

5

ICS9148-11

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (Default=0)

General I2C serial interface information

BIT PIN# DESCRIPTION PWD

Bit 7 - Reserved 0
Bit 6 - Must be 0 for normal operation 0

Bit 5

- Must be 0 for normal operation 0
In Spread Spectrum, Controls type
(0=centered, 1=down spread)

0

Bit 4

- Must be 0 for normal operation 0
In Spread Spectrum, Contro ls Spreading
(0=1.8%, 1=0.6%)

0

Bit 3 - Reserved 0
Bit 2 - Reserved 0
Bit 1
Bit 0

-

Bit1

1
1
0
0

Bit0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
0 - Normal operation

0
0

Note: PWD = Power-Up Default

A. For the clock generator to be addressed by an I

2

C controller, the following address must be sent as a start sequence,

with an acknowledge bit between each byte.

B. The clock generator is a slave/receiver I

2

C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.

C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

D. The input is operating at 3.3V logic levels.

E. The data byte format is 8 bit bytes.

F. To simplify the clock generator I

2

C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.

G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

to a 1 (Enabled output state)

Then Byte 0, 1, 2, etc in
sequence until STOP.

Byte 0, 1, 2, etc in sequence until STOP.

Clock Generator

Address (7 bits)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

D2

(H)

Clock Generator

Address (7 bits)

ACK

Byte 0 ACK Byte 1 ACK

A(6:0) & R/W#

D3

(H)