ICS (Now IDT) ICS1524AM Schematic [ru]
Integrated
Circuit
ICS1524A
Systems, Inc.
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description Features
The ICS1524A is a low-cost, very high-performance
frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
genlocked applications.
The ICS1524A offers two channels of clock phase controlled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’ s input
and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input
signal.
Optionally , the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
The advanced PLL uses either its internal programmable feedback divider or an external divider and is
programmed by a standard I
2
C-bus™ serial interface.
• Wide input frequency range
• 8 kHz to 100 MHz
• 250 MHz balanced PECL differential outputs
• 150 MHz single-ended SSTL_3 clock outputs
• Dynamic Phase Adjust (DPA) for DPACLK
outputs
• Software controlled phase adjustment
• 360
o
Adjustment down to 1/64 clock
increments
• External or internal loop filter selection
• Uses 3.3 VDC Inputs are 5 volt tolerant.
2
C-bus serial interface runs at either low speed
•I
(100 kHz) or high speed (400 kHz).
• Hardware and Software PLL Lock detection
Applications
• Generic Frequency Synthesis
• LCD Monitors and Projectors
• Genlocking Multiple Video Systems
Block Diagram
HSYNC
OSC
2
IC
I2C-bus is a trademark of Philips Corporation.
ICS1524A Rev D 12/23/2005
Loop
Filter
CLK
CLK+/-
DPACLK
DPACLK+/-
FUNC
Pin Configuration
VDDD
VSSD
SDA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
1
2
3
4
5
6
7
8
9
10
11
12
24 Pin 300-mil SOIC
24
23
22
21
20
19
18
ICS1524A
17
16
15
14
13
IREF
CLK+ (PECL)
C
LK– (PECL)
DPACLK+ (PECL)
DPACLK– (PECL)
VSSQ
VDDQ
CLK (SSTL)
DPA
CLK (SSTL)
FUNC (SSTL)
LOCK/REF (SSTL)
2
ICADR
ICS 1524A
Document Revision History
Rev A
ICS1523 Rev T Datasheet used as a starting template
New Block Diagram substituted for old 1523 one
Removed reference to CLK / 2 Functionality
Created a set of clock outputs that bypass the DPA
External PDEN is now the IN-SEL MUX control bit
Text descriptions changed to support new 1524 block diagram
Rev B
Replaced page 15 “Layout Guidelines”
Replaced SIOC Package diagram on page 22
“Advanced Status” removed
Redrew front page graphics for clairity
Rev C
Corrected Chip Revision and Chip Version values on page 5
Changed Title on Page 1
Minor format changes to pages 8 and 21
Corrected pin names on page 10
Rev D Miscellaneous updates to Block Diagram on page 3
Changed reference from “Phase Detector” to “Charge Pump”. Pages 4-7, 10
ICS1524A Rev D 12/23/2005
2
Block Diagram
DPACLK
DPACLK-
DPACLK+
CLK
CLK+
ICS1524A
CLK-
EnPLS
Reg 0:6
EnDLS
Reg 0:7
PDEN
PDEN
Reg 0x0:0
PD_Pol
Reg 0x0:1
PSD
Reg 0x1:4-5
POST
SCALER
Fill_Sel
Reg 0x4:7
PFD
Out_Scl
Reg 0x6:6-7
Divider
Reg 0x1:0-2
REG 12:1
PLL_LOCK
REG 12:0
DPA_LOCK
OE_Tck
Reg 0x6:1
OE_Pck
DPA_OS
Reg 0x4:0-5
Reg 0x6:0
DPA_Res
Reg 0x5:0-1
FBD
Reg 0x3:0-3
FBD
OE_T2
Reg 0x6:3
Reg 0x2:0-7
OE_P2
MUX
Func_Sel
Reg 0x0:5
Reg 0x6:2
Ck2_Inv
Reg 6:5
OE_F
Reg 0x6:4
LOCK/REF
Osc_Div
Reg 0x7:0-6
Ref_Pol
Reg 0x0:2
In_Sel
Reg 0x7:7
Fbk_Pol
Fbk_Sel
Reg 0x0:4
Reg 0x0:3
ICS1524A Rev D 12/23/2005
3
ICS 1524A
Pin Descriptions
.ONNIPEMANNIPEPYTNOITPIRCSEDSTNEMMOC
1DDDVRWPylppuslatigiDsnoitceslatigidotV3.3
2DSSVRWPdnuorglatigiDsnoitceslatigi
3ADSTUO/NIatadlaireSI
4LCSNIkcolclaireSI
2
2
5NEDPNIpmuPegrahCpmupegrahcsdnepsuS
6BFTXENIkcabdeeflanretxEottupniredividlanretxEDFP
7CNYSHNIcnyslatnoziroHLLPottupnikcolC
8LIFTXENIretliflanretxEretlifpoolLLPlanretxE
9TERLIFXNInruterretliflanretxEnruterretlifpoolLLPlanretxE
01ADDVRWPyl
ppusgolanAyrtiucricgolanarofV3.3
11ASSVRWPdnuorggolanAyrtiucricgolanarofdnuorG
21CSONIrotallicsOrotallicsolatsyr
31I2RDACNII2sserddaC
41FER/KCOLLTSSecnerefer/rotacidnikcoLtupniFERrokco
51CNUFLTSStuptuonoitcnuFtuptuoCNYSHelbatceles3_LTSS
61KLCLTSStkcolclexiPkcolC3_LTSSdeyaleD-no
N
71KLCAPDLTSSkcolCdeyaleDAPDkcolC3_LTSSdeyaleDAPD
81QDDVRWPylppusrevirdtuptuOsrevirdtuptuorofDDVV3.3
91QSSVRWPdnuo
02–KLCAPDLCEP-kcolcLCEPdeyaleDAPD .niardnepOkcolCLCEPdetrevnIdeyaleDAP
rgrevirdtuptuOsrevirdtuptuorofdnuorG
D
12+KLCAPDLCEP+kcolcLCEPdeyaleDAPD .niardnepOkcolCLCEPdeyaleDAPD
22–KLCLCEP-kcolcLCEP .niardnepOkcolCLCEPdetre
32+KLCLCEP+kcolcLCEP .niardnepOkcolCLCEPdeyaleD-noN
42FERINItnerrucecnerefeRstuptuoLCEProftnerru
drofdnuorG
1
sub-C
1
sub-C
cmorftupnIegakcap
2
IpihC
cecnerefeR
1
1
1
2,1
tcelessserddaC
etirwhC4,daerhD4=woL
etirwhE4,daerhF4=hgiH
lAPDroLLPsyalpsiD
vnIdeyaleD-noN
Notes:
1. These L VTTL input s are 5 V -tolerant.
2. Connect to ground if unused.
ICS1524A Rev D 12/23/2005
4
ICS1524A
I2C Register Map Summary
Register
Index
0h Input Control R / W PDen 0 1 Charge Pump Enable (0=Disable 1=Enable)
1h Loop Control R / W * PFD0-2 0-2 0 Charge Pump Gain
2h FdBk Div 0 R / W * FBD0-7 0-7 FF PLL FeedBack Divider LSBs (bits 0-7) *
3h FdBk Div 1 R / W * FBD8-11 0-3 F PLL Feedback Divider MSBs (bits 8-11) *
Name Access Bit Name Bit #
PD_Pol 1 0 Cha rge Pum p Enable Polarity
Ref_Pol 2 0 External Reference Polarity (0=Positive Edge, 1=Negative Edge)
Fbk_Pol 3 0 External Feedb ack Polarit y (0=Positive Edge, 1=Negative Edge)
Fbk_Sel 4 0 External Feedback Selec t (0=Internal Feedback, 1=External)
Func_Sel 5 0 Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)
EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)
EnDLS 7 0 Enable DPA Lock/Ref Status Output (0=Disable 1=Enable)
Reserved 3 0 Reserved
PSD0-1 4-5 0 Post-Scaler Divider (0 = /2, 1 = /4, 2 = /8, 3 = /16)
Reserved 6-7 0 Reserved
Reserved 4-7 0 Reserved
Reset
Value
Description
4h DPA Offset R / W DPA_OS0-5 0-5 0 Dynamic Phase Aligner Offset
Reserved 6 0 Reserved
Fil_Sel 7 1 Loop Filter Select (0=External, 1=Internal)
5h DPA Control R / W ** DPA_Res0-1 0-1 3 DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal_Rev 2-7 0 Metal Mask Revision Number
6h Output Enables R / W OE_Pck 0 1 Output Enable for PECL DPACLK ( 0=High Z, 1=Enabled)
OE_Tck 1 1 Output Enable for STTL_3 DPACLK ( 0=High Z, 1=Enabled)
OE_P2 2 1 Output Enable for PECL CLK ( 0=High Z, 1=Enabled)
OE_T2 3 1 Output Enable for STTL_3 CLK ( 0=High Z, 1=Enabled)
OE_F 4 1 Output Enable for STTL_3 FUNC ( 0=High Z, 1=Enabled)
Ck2_Inv 5 0 Select non-delayed CLK (1) or DPA delayed CLK/ 2 (0) on CLK x pins
Out_Scl 6-7 0 SSTL DPACLK (Pin 17) Sc aler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
7h Osc_Div R / W Osc_Div 0-6 0-6 0 Osc Divider modulus
In-Sel 7 1 RESERVED
8h Reset Write DPA 0-3 x Writing xA hex resets DPA and loads working register 5
PLL 4-7 x Writing 5x hex resets PLL and loads working registers 1-3
10h Chip Ver Rea d Chip Ver 0- 7 18 Chip Version 17 hex
11h Chip Rev Read Chip Rev 0-7 01 Chip Revision C2 hex
12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked)
PLL_Lock 1 N/A PLL Lock Status (0=Unlocked, 1=Locked)
Reserved 2-7 0 Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
5
ICS1524A Rev D 12/23/2005
ICS 1524A
Detailed Register Description
Name: Input Control
Register: 0 h
Index: Read / Write
Bit Name Bit # Reset Value Description
PDen 0 1 Charge Pump Enable
PD_Pol 1 0 Charge Pump Enable Polarity
Ref_Pol 2 0 External Reference Polarity
Fbk_Pol 3 0 External Reference Feedback Polarity
Fbk_Sel 4 0 External Feedback Select
Func_Sel 5 0 Function Output Select
EnPLS 6 1 Enable PLL Lock Status Output on LOCK/REF pin
EnDLS 7 0 Enable DPA Lock Status Output on LOCK/REF pin
Bit Name Description
0 PDen Charge Pump Enable
0 = External Enable via PDEN pin
1 = Always Enable
1 PD_Pol Charge Pump Enable Polarity
0 = Active High
1 = Active Low
2 Ref_Pol External Reference Polarity —
Edge of input signal on which Phase/Frequency Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3 Fbk_Pol External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4 Fbk_Sel External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
5 Func_Sel Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6 EnPL S Enable LOCK/REF (pin14) Output
7 EnDLS
ICS1524A Rev D 12/23/2005
SLPnESLDnELES_NI)41(FER/KCOL
00 A/N0
01 A/Nesiwrehto0,dekcolAPDfi1
10 A/Nesiwrehto0,dekcolLLPfi1
110
111 F
÷ viD_csO
cso
6
reggirtttimhcStsoP
feRROX)7(CNYSH
loP_
Name: Loop Control Register
Register: 1h
Index: Read / Write*
Bit Name Bit # Reset Value Description
PFD0-2 0-2 0 Charge Pump Gain
Reserved 3 0 Reserved
PSD0-1 4-5 0 Post-Scaler Divider
Reserved 6-7 0 Reserved
Bit Name Description
0-2 PFD0-2 Charge Pump Gain
2tiB1tiB0tiB2/Aµ(niaGCP π )dar
000 1
001 2
010 4
011 8
100 61
10 1 23
110 46
111 82
ICS1524A
1
3 Reserved
4-5 PSD0-1 Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.
5tiB4tiBrediviDDSP
00 )tluafed(2
01 4
10 8
11 61
6-7 Reserved
Double-buffered register . Actual working registers are loaded during software PLL reset.
*
See register 8h for details.
7
ICS1524A Rev D 12/23/2005
ICS 1524A
Name: Feedback Divider 0 Register / Feedback Divider 1 Register
Register: 2h, 3h
Index: Read /Write*
Bit Name Index Bit # Reset Value Description
FBD0-7 2 0-7 FF PLL Feedback Divider LSBs (0-7).* When Bit 0 = 0, then the total
number of clocks per line is even. When Bit 0 = 1, then the total
number of clocks is odd.
FBD8-11 3 0 -3 F PLL Feedback Divider MSBs (8-11)*
Reserved 3 4-7 Reserved
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
3geR2geR
321076543210
Feedback Divider Modulus
=
12 ≤ Feedback Divider Modulus ≤ 4103
+8
Double-buffered registers. Actual working registers are loaded during software PLL reset.
*
See Register 8h for details.
Name: DPA Offset Register
Register: 4 h
Index: Read /Write
Bit Name Bit # Reset Value Description
DPA_OS0-5 0-5 0 Dynamic Phase Adjust Of fset
Reserved 6 0 Reserved
Fil_Sel 7 0 Loop Filter Select
Bit Name Description
0-5 DPA_OS0-5 Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7 Fil_Sel Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Typical loop filter
values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor,
and 33 pF for the shunt capacitor.
ICS1524A Rev D 12/23/2005
8
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