ICSI IS61LV6464-7TQ, IS61LV6464-6TQ, IS61LV6464-8TQ, IS61LV6464-6PQ, IS61LV6464-100TQ Datasheet

IS61LV6464

Integrated Circuit Solution Inc. 1

SSR010-0B

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

• Fast access time:
– 5 ns-100 MHz; 6 ns-83 MHz;

7 ns-75 MHz; 8 ns-66 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and
control

• Pentium™ or linear burst sequence control
using MODE input

• Five chip enables for simple depth expansion
and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 128-Pin LQFP and PQFP 14mm x
20mm package

• Single +3.3V power supply

• 2.5V V

CCQ (I/O supply)

• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND

Q

or VCCQ to alter their power-up state

DESCRIPTION

The ICSI IS61LV6464 is a high-speed, low-power synchro­nous static RAM designed to provide a burstable, high-perfor­mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with ICSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con­trolled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con­trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49­I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61LV6464 and controlled by the ADV (burst address
advance) input pin.

Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GND

Q, on MODE pin

selects LINEAR Burst. A VCCQ (or no connect) on MODE pin
selects INTERLEAVED Burst.

IS61LV6464

64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM

IS61LV6464

2 Integrated Circuit Solution Inc.

SSR010-0B

BLOCK DIAGRAM

16

BINARY

COUNTER

A15-A0

BW1

GW

CLR

CE

CLK

Q0

Q1

MODE

A0’

A0

A1

A1’

CLK

ADV

ADSC
ADSP

14 16

ADDRESS

REGISTER

CE

D

CLK

Q

DQ57-DQ64

BYTE WRITE

REGISTERS

D

CLK

Q

DQ8-DQ1

BYTE WRITE

REGISTERS

D

CLK

Q

ENABLE

REGISTER

CE

D

CLK

Q

ENABLE

DELAY

REGISTER

D

CLK

Q

BWE

BW8

CE

CE2

CE2

CE3

CE3

64K x 64

MEMORY

ARRAY

64

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

64

OE

8

64

OE

DATA[64:1]

IS61LV6464

Integrated Circuit Solution Inc. 3

SSR010-0B

PIN CONFIGURATION

128-Pin LQFP and PQFP

VCCQ
I/O

32

I/O

31

I/O

30

I/O

29

I/O

28

I/O

27

I/O

26

I/O

25

I/O

24

I/O

23

I/O

22

GNDQ
VCCQ
I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

GNDQ
VCCQ
I/O

11

I/O

10

I/O

9

I/O

8

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

GNDQ

VCCQ

CE3

CE2

CE3

CE2

GND

VCCCEBW8

BW7

BW6

BW5OECLK

BWEGWBW4

BW3

GND

VCC

BW2

BW1

ADSC

ADSP

ADV

GNDQ

GNDQ

I/O

33

I/O

34

I/O

35

I/O

36

I/O

37

I/O

38

I/O

39

I/O

40

I/O

41

I/O

42

I/O

43

VCCQ
GNDQ

I/O

44

I/O

45

I/O

46

I/O

47

I/O

48

I/O

49

I/O

50

I/O

51

I/O

52

I/O

53

VCCQ
GNDQ

I/O

54

I/O

55

I/O

56

I/O

57

I/O

58

I/O

59

I/O

60

I/O

61

I/O

62

I/O

63

I/O

64

VCCQ

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

GNDQNCMODE

A15

A14

A13

VCC

GND

A12

A11

A10

A9

A8NCA7A6A5A4A3

VCC

GND

A2A1A0

ZZ

VCCQ

39404142434445464748495051525354555657585960616263

64

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

PIN DESCRIPTIONS

A0-A15 Address Inputs

CLK Clock

ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW8 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE, CE2, CE2, Synchronous Chip Enable

CE3, CE3
OE Output Enable

DQ1-DQ64 Data Input/Output

ZZ Sleep Mode

MODE Burst Sequence Mode

VCC +3.3V Power Supply

GND Ground

VCCQ Isolated Output Buffer Supply:

+2.5V

NC No Connect

GNDQ Isolated Output Buffer Ground

IS61LV6464

4 Integrated Circuit Solution Inc.

SSR010-0B

TRUTH TABLE

ADDRESS

OPERATION USED CE3 CE2

CE3CE3

CE3CE3

CE3

CE2CE2

CE2CE2

CE2

CECE

CECE

CE

ADSPADSP

ADSPADSP

ADSP

ADSCADSC

ADSCADSC

ADSC

ADVADV

ADVADV

ADV

WRITEWRITE

WRITEWRITE

WRITE

OEOE

OEOE

OE CLK I/O

Deselected, Power-down None X X X X H X L X X X L-H High-Z

Deselected, Power-down None L X X X L L XXXXL-HHigh-Z

Deselected, Power-down None X L X X L L XXXXL-HHigh-Z

Deselected, Power-down None X X H X L L XXXXL-HHigh-Z

Deselected, Power-down None X X X H L L XXXXL-HHigh-Z

Deselected, Power-down None L X X X L H L X X X L-H High-Z

Deselected, Power-down None X L X X L H L X X X L-H High-Z

Deselected, Power-down None X X H X L H L X X X L-H High-Z

Deselected, Power-down None X X X H L H L X X X L-H High-Z

Read Cycle, Begin Burst External H H L L L L X X X L L-H Dout

Read Cycle, Begin Burst External H H L L L L X X X H L-H High-Z

Write Cycle, Begin Burst External H H L L L H L X L X L-H Din

Read Cycle, Begin Burst External H H L L L H L X H L L-H Dout

Read Cycle, Begin Burst External H H L L L H L X H H L-H High-Z

Read Cycle, Continue Burst Next X X X X X H H L H L L-H Dout

Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z

Read Cycle, Continue Burst Next X X X X H X H L H L L-H Dout

Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z

Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din

Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din

Read Cycle, Suspend Burst Current X X X X X HHHHLL-HDout

Read Cycle, Suspend Burst Current X X X X X HHHHHL-HHigh-Z

Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout

Read Cycle, Suspend Burst Current X X X X H X HHHHL-HHigh-Z

Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din

Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din

Notes:

1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2. Wait states are inserted by suspending burst.

3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.

4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.

5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

IS61LV6464

Integrated Circuit Solution Inc. 5

SSR010-0B

ASYNCHRONOUS TRUTH TABLE

Operation ZZ

OEOE

OEOE

OE I/O STATUS

Pipelined Read L L Dout
Pipelined Read L H High-Z
Write L L High-Z
Write L H Din

Deselect L X High-Z

Sleep H X High-Z

WRITE TRUTH TABLE

Operation

GWGW

GWGW

GW

BWEBWE

BWEBWE

BWE

BW8BW8

BW8BW8

BW8

BW7BW7

BW7BW7

BW7

BW6BW6

BW6BW6

BW6

BW5BW5

BW5BW5

BW5

BW4BW4

BW4BW4

BW4

BW3BW3

BW3BW3

BW3

BW2BW2

BW2BW2

BW2

BW1BW1

BW1BW1

BW1

Read H H X X X X X X X X

Read H L H H H H H H H H

Write all bytes H L L L L L L L L L

Write all bytes L X X X X X X X X X

Write Byte 1 H L H H H H H H H L

Write Byte 2 H L H H H H H H L H

Write Byte 3 H L H H H H H L H H

Write Byte 4 H L H H H H L H H H

Write Byte 5 H L H H H L H H H H

Write Byte 6 H L H H L H H H H H

Write Byte 7 H L H L H H H H H H

Write Byte 8 H L L H H H H H H H

IS61LV6464

6 Integrated Circuit Solution Inc.

SSR010-0B

INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

1,0

0,1A1’, A0’ = 1,1

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.0 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V

for Address and Control Inputs

VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.