Page 1
IS61C632A
IS61C632A
32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
FEATURES
• Fast access time:
– 4 ns-125 MHZ; 5 ns-100 MHz;
6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or VCCQ to alter their power-up state
Q
DESCRIPTION
The ICSI IS61C632A is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the i486™, Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 32,768
words by 32 bits, fabricated with ICSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61C632A and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc. 1
SSR001-0B
Page 2
IS61C632A
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
CLK
BINARY
COUNTER
CE
CLR
Q0
Q1
MODE
A0
A1
A0’
A1’
32K x 32
MEMORY
ARRAY
A14-A0
GW
BWE
BW4
BW3
BW2
BW1
15
D
Q
13 15
ADDRESS
REGISTER
CE
CLK
D
Q
32
32
DQ32-DQ25
BYTE WRITE
REGISTERS
CLK
D
Q
DQ24-DQ17
BYTE WRITE
REGISTERS
CLK
D
Q
DQ16-DQ9
BYTE WRITE
REGISTERS
CLK
D
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE1
CE2
CE3
D
ENABLE
REGISTER
CE
CLK
D
Q
Q
4
REGISTERS
INPUT
CLK
OUTPUT
REGISTERS
CLK
OE
32
DATA[32:1]
ENABLE
DELAY
REGISTER
CLK
OE
2 Integrated Circuit Solution Inc.
SSR001-0B
Page 3
IS61C632A
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
A6A7CE1
CE2
BW4
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
NC
NC
NC
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
BW3
BW2
BW1
CE3
VCC
GND
CLKGWBWEOEADSC
ADSP
46 47 48 49 50
ADVA8A9
80
NC
79
DQ16
78
DQ15
77
VCCQ
76
GNDQ
75
DQ14
74
DQ13
73
DQ12
72
DQ11
71
GNDQ
70
VCCQ
69
DQ10
68
DQ9
67
GND
66
NC
65
VCC
64
ZZ
63
DQ8
62
DQ7
61
VCCQ
60
GNDQ
59
DQ6
58
DQ5
57
DQ4
56
DQ3
55
GNDQ
54
VCCQ
53
DQ2
52
DQ1
51
NC
A5A4A3A2A1
MODE
A0
NC
NC
PIN DESCRIPTIONS
A0-A14 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW4 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE1, CE2, CE3 Synchronous Chip Enable
GND
VCC
NC
NC
NC
A13
A14
NC
A10
A11
A12
OE Output Enable
DQ1-DQ32 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V
GNDQ Isolated Output Buffer Ground
Integrated Circuit Solution Inc. 3
SSR001-0B
Page 4
IS61C632A
TRUTH TABLE
ADDRESS
OPERATION USED
CE1CE1
CE1 CE2
CE1CE1
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X H L X X X High-Z
Deselected, Power-down None L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst External L H L L X X X H High-Z
Write Cycle, Begin Burst External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst External L H L H L X H H High-Z
Read Cycle, Continue Burst Next X X X H H L H L Q
Read Cycle, Continue Burst Next X X X H H L H H High-Z
Read Cycle, Continue Burst Next H X X X H L H L Q
Read Cycle, Continue Burst Next H X X X H L H H High-Z
Write Cycle, Continue Burst Next X X X H H L L X D
Write Cycle, Continue Burst Next H X X X H L L X D
Read Cycle, Suspend Burst Current X X X HHHH LQ
Read Cycle, Suspend Burst Current X X X HHHHHHigh-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X HHHHHigh-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
CE3CE3
CE3
CE3CE3
ADSPADSP
ADSP
ADSPADSP
ADSCADSC
ADSC
ADSCADSC
ADVADV
ADV
ADVADV
WRITEWRITE
WRITE
WRITEWRITE
OEOE
OE DQ
OEOE
PARTIAL TRUTH TABLE
FUNCTION GW BWE BW1 BW2 BW3 BW4
READ H H X X X X
READ H X H H H H
WRITE Byte 1 H L L H H H
WRITE All Bytes X LLLLL
WRITE All Bytes L XXXXX
4 Integrated Circuit Solution Inc.
SSR001-0B
Page 5
IS61C632A
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
0,1A1’, A0’ = 1,1
1,0
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.8 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
(1)
Integrated Circuit Solution Inc. 5
SSR001-0B
Page 6
IS61C632A
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
I
LI Input Leakage Current GND ≤ VIN ≤ VCCQ
(2)
Com. –5 5 µA
Ind. –10 1-
LO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. –5 5 µA
I
Ind. –10 10
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Test Conditions
ICC AC Operating Device Selected, Com. 150 180 140 170 130 160 120 150 110 140 mA
Supply Current All Inputs = VIL or VIH Ind. — — — — 140 170 130 160 120 150 µA
OE = VIH,
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 15 45 15 45 15 45 15 45 15 45 mA
VCC = Max., Ind. — — — — 20 50 20 50 20 50 µA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
Typ. Max Typ. Max. Typ. Max. Typ. Max. Typ. Max. Uni
t
IZZ Power-Down Mode ZZ = VCCQ, CLK Running Com. 1 10 1 10 1 10 1 10 1 10 mA
Current All Inputs ≤ GND + 0.2V Ind. — — — — 2 20 2 20 2 20 mA
or ≥ VCC – 0.2V
Note:
1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to
CCQ.
V
2. MODE pin should be tied to Vcc or GND. They exhibit ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc –
0.2V.
6 Integrated Circuit Solution Inc.
SSR001-0B
Page 7
IS61C632A
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Output
Buffer
O
= 50Ω
Z
Figure 1
30 pF
1.25V
50Ω
2.5V
OUTPUT
5 pF
Including
jig and
scope
Figure 2
317 Ω
351 Ω
Integrated Circuit Solution Inc. 7
SSR001-0B
Page 8
IS61C632A
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8 ns
(2)
tKQX
tKQLZ
tKQHZ
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns
(2,3)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns
tOEQ Output Enable to Output Valid — 4 — 5 — 6 — 6 — 6 ns
(2)
tOEQX
tOELZ
tOEHZ
Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
(1)
25 — 35 — 45 — 66.7 — 80 — ns
8 Integrated Circuit Solution Inc.
SSR001-0B
Page 9
IS61C632A
READ CYCLE TIMING
CLK
t
SS
ADSP
t
SH
t
KH
t
KC
t
KL
ADSP is blocked by CE1 inactive
ADSC
ADV
A14-A0
GW
BWE
BW4-BW1
CE1
CE2
t
AS
t
AH
RD1 RD2
t
WS
t
WS
t
CES
t
CES
t
CEH
t
CEH
t
SS
t
AVS
t
SH
t
AVH
Suspend Burst
ADSC initiate read
RD3
t
WH
t
WH
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
t
CES
t
CEH
CE3
t
t
OEQ
OEHZ
OE
t
KQX
t
KQHZ
DATA
OUT
DATA
IN
High-Z
High-Z
t
OELZ
t
KQLZ
t
KQ
t
OEQX
1a
2a 2b
2c 2d 3a
Pipelined Read
Single Read
Burst Read
Unselected
Integrated Circuit Solution Inc. 9
SSR001-0B
Page 10
IS61C632A
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
(1)
25 — 35 — 45 — 52 — 60 — ns
10 Integrated Circuit Solution Inc.
SSR001-0B
Page 11
IS61C632A
WRITE CYCLE TIMING
CLK
t
SS
ADSP
ADSC
ADV must be inactive for ADSP Write
ADV
t
AS
t
SH
t
AH
t
KH
t
KC
t
KL
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
t
AVS
AVH
A14-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
OE
WR1 WR2
t
WS
t
WS
t
WS
WR1 WR2
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
WH
t
WH
t
WH
WR3
t
WS
t
WH
WR3
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
DATA
OUT
DATA
IN
High-Z
t
High-Z
Single Write
DS
1a
t
DH
BW4-BW1 only are applied to first cycle of WR2
2c 2d2b2a
Burst Write
Write
3a
Unselected
Integrated Circuit Solution Inc. 11
SSR001-0B
Page 12
IS61C632A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8 ns
(2)
tKQX
tKQLZ
tKQHZ
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns
(2,3)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns
tOEQ Output Enable to Output Valid — 4.5 — 4.8 — 6 — 6 — 6 ns
(2)
tOEQX
tOELZ
tOEHZ
Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(2,3)
Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
(1)
25 — 35 — 45 — 52 — 60 — ns
12 Integrated Circuit Solution Inc.
SSR001-0B
Page 13
IS61C632A
READ/WRITE CYCLE TIMING
CLK
t
t
SH
t
KH
t
AH
ADSP
ADSC
ADV
t
SS
t
AS
t
SS
KC
t
KL
t
SH
ADSP is blocked by CE1 inactive
A14-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
OE
RD1 WR1
t
WS
t
WS
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
OEQ
t
WH
t
WH
RD2 RD3
t
WS
t
WH
WR1
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
t
OEHZ
Unselected with CE3
t
KQX
t
KQHZ
Unselected
DATA
OUT
DATA
IN
High-Z
High-Z
t
OELZ
t
KQLZ
t
Single Read
KQ
t
OEQX
1a
t
KQX
t
KQHZ
t
DS
Single Write
1a
t
2a 2b 2c 2d
DH
Burst Read
Integrated Circuit Solution Inc. 13
SSR001-0B
Page 14
IS61C632A
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8 ns
(4)
tKQX
tKQLZ
tKQHZ
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns
(4,5)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(4,5)
Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns
tOEQ Output Enable to Output Valid — 4.5 — 5 — 6 — 6 — 6 ns
(4)
tOEQX
tOELZ
tOEHZ
Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns
(4,5)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
(4,5)
Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby
tZZREC ZZ Recovery
tCFG Configuration Setup
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with the load in Figure 2.
(1)
(2)
(3)
2— 2— 2— 2— 2—cyc
2— 2— 2— 2— 2—cyc
25 — 35 — 45 — 52 — 60 — ns
14 Integrated Circuit Solution Inc.
SSR001-0B
Page 15
IS61C632A
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
t
KL
ADSP
ADSC
ADV
A14-A0
GW
t
t
SS
t
AS
KH
t
SH
t
AH
RD1
RD2
BWE
BW4-BW1
CE1
CE2
CE3
OE
DATA
OUT
DATA
IN
t
CES
t
CES
t
CES
High-Z
High-Z
t
CEH
t
CEH
t
CEH
t
KQLZ
t
OEQ
t
OELZ
t
KQ
t
OEQX
1a
t
KQX
t
KQHZ
t
OEHZ
t
ZZS
t
ZZREC
ZZ
Single Read
Snooze with Data Retention
Read
Integrated Circuit Solution Inc. 15
SSR001-0B
Page 16
IS61C632A
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part Number Package
4 IS61C632A-4TQ 14*20*1.4mm LQFP
4 IS61C632A-4PQ 14*20*2.7mm PQFP
5 IS61C632A-5TQ 14*20*1.4mm LQFP
5 IS61C632A-5PQ 14*20*2.7mm PQFP
6 IS61C632A-6TQ 14*20*1.4mm LQFP
6 IS61C632A-6PQ 14*20*2.7mm PQFP
7 IS61C632A-7TQ 14*20*1.4mm LQFP
7 IS61C632A-7PQ 14*20*2.7mm PQFP
8 IS61C632A-8TQ 14*20*1.4mm LQFP
8 IS61C632A-8PQ 14*20*2.7mm PQFP
Industrial Range: –40°C to +85°C
Speed (ns) Order Part Number Package
6 IS61C632A-6TQI 14*20*1.4mm LQFP
6 IS61C632A-6PQI 14*20*2.7mm PQFP
7 IS61C632A-7TQI 14*20*1.4mm LQFP
7 IS61C632A-7PQI 14*20*2.7mm PQFP
8 IS61C632A-8TQI 14*20*1.4mm LQFP
8 IS61C632A-8PQI 14*20*2.7mm PQFP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
16 Integrated Circuit Solution Inc.
SSR001-0B
Loading...