ICSI IS41C16100S, IS41LV16100S User Manual

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IS41C16100S
IS41LV16100S

1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE

FEATURES

• Extended Data-Out (EDO) Page Mode access cycle

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval:
Refresh Mode: 1,024 cycles /16 ms
RAS-Only, CAS-before-RAS (CBR), and Hidden
Self refresh Mode - 1,024 cycles / 128ms

• JEDEC standard pinout

• Single power supply:
5V ± 10% (IS41C16100S)

3.3V ± 10% (IS41LV16100S)

• Byte Write and Byte Read operation via two CAS

• Industrail Temperature Range -40°C to 85°C

EY TIMING PARAMETERS

Parameter -45

Max. RAS Access Time (tRAC) 455060ns
Max. CAS Access Time (tCAC) 111315ns

Max. Column Address Access Time (tAA)222530ns

Min. EDO Page Mode Cycle Time (tPC)162025ns

Min. Read/Write Cycle Time (tRC) 77 84 104 ns

(1)

DESCRIPTION

The ICSI IS41C16100S and IS41LV16100S are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. These devices offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 1,024 ran­dom accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of upper
and lower byte, makes the IS41C16100S ideal for use in
16-, 32-bit wide data bus systems.

These features make the IS41C16100Sand IS41LV16100S
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.

The IS41C16100S and IS41LV16100S are packaged in a
42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.

-50 -60 Unit

Note:

1. 45 ns Only for Vcc = 3.3V.

PIN CONFIGURATIONS

50(44)-Pin TSOP II

50

GND

49

I/O15

48

I/O14

47

I/O13

46

I/O12

45

GND

44

I/O11

43

I/O10

42

I/O9

41

I/O8

40

NC

36

NC

35

LCAS

34

UCAS

33

OE

32

A9

31

A8

30

A7

29

A6

28

A5

27

A4

26

GND

I/O0
I/O1
I/O2
I/O3

I/O4
I/O5
I/O6
I/O7

NC

NC
NC

WE

NC
NC

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11

15
16
17
18
19
20
21
22
23
24
25

VCC

VCC

RAS

VCC

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

42-Pin SOJ

1

VCC

2

I/O0

3

I/O1

4

I/O2

5

I/O3

6

VCC

7

I/O4

8

I/O5

9

I/O6

10

I/O7

11

NC

12

NC

13

WE

14

RAS

15

NC

16

NC

17

A0

18

A1

19

A2

20

A3

21

VCC

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND

PIN DESCRIPTIONS

A0-A9 Address Inputs

I/O0-15 Data Inputs/Outputs

WE Write Enable

OE Output Enable

RAS Row Address Strobe

UCAS Upper Column Address Strobe

LCAS Lower Column Address Strobe

Vcc Power

GND Ground

NC No Connection

Integrated Circuit Solution Inc. 1

DR004-0B

IS41C16100S
IS41LV16100S

FUNCTIONAL BLOCK DIAGRAM

OE
WE

LCAS

UCAS

RAS

A0-A9

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS

BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

1,048,576 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

2 Integrated Circuit Solution Inc.

DR004-0B

IS41C16100S
IS41LV16100S

TRUTH TABLE

Function

RASRAS

RAS

RASRAS

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN

Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Read-Write
EDO Page-Mode Read

(1,2)

LLLH

(2)

1st Cycle: L H→LH→L H L ROW/COL DOUT
2nd Cycle: L H→LH→L H L NA/COL DOUT
Any Cycle: L L→HL→H H L NA/NA DOUT

EDO Page-Mode Write

(1)

1st Cycle: L H→LH→L L X ROW/COL DIN
2nd Cycle: L H→LH→L L X NA/COL DIN

EDO Page-Mode

(1,2)

1st Cycle: L H→LH→LH→LL→H ROW/COL DOUT, DIN

Read-Write 2nd Cycle: L H→LH→LH→LL→H NA/COL DOUT, DIN

Write

(2)

L→H→L L L H L ROW/COL DOUT

(1,3)

L→H→L L L L X ROW/COL DOUT

Hidden Refresh Read

RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

(4)

H→L L L X X X High-Z

LCASLCAS

LCAS

LCASLCAS

UCASUCAS

UCAS

UCASUCAS

WEWE

WE

WEWE

OEOE

OE Address tR/tC I/O

OEOE

Upper Byte, High-Z

Upper Byte, DOUT

Upper Byte, High-Z

Upper Byte, DIN

→

LL→H ROW/COL DOUT, DIN

Integrated Circuit Solution Inc. 3

DR004-0B

IS41C16100S
IS41LV16100S

Functional Description

The IS41C16100S and IS41LV16100S is a CMOS DRAM
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 16 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter ten bits.

The IS41C16100S and IS41LV16100S has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden­tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.

The IS41C16100S and IS41LV16100S CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16100S and IS41LV16100S both
BYTE READ and BYTE WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever
occurs first.

Refresh Cycle

To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1,024 row addresses (A0

through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re­freshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before­RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row

addresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.

The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.

However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the re­sumption of normal operation.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.

In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS
cycle time becomes shorter.

In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.

The EDO page mode allows both read and write opera­tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial­ization cycles (any combination of cycles containing a
RAS signal).

During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.

4 Integrated Circuit Solution Inc.

DR004-0B

IS41C16100S
IS41LV16100S

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

V

T Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V

3.3V –0.5 to +4.6

CC Supply Voltage 5V –1.0 to +7.0 V

V

3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70 °C

Industrial Operationg Temperature –40 to +85 °C

TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V

3.3V 3.0 3.3 3.6

VIH Input High Voltage 5V 2.4 — VCC + 1.0 V

3.3V 2.0 — VCC + 0.3

VIL Input Low Voltage 5V –1.0 — 0.8 V

3.3V –0.3 — 0.8

TA Commercial Ambient Temperature 0 — 70 °C

Industrial Ambient Temperature –40 — 85 °C

CAPACITANCE

(1,2)

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz.

Integrated Circuit Solution Inc. 5

DR004-0B

IS41C16100S
IS41LV16100S

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

I

IL Input Leakage Current Any input 0V < VIN < Vcc –5 5 µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –5 5 µA

0V < VOUT < Vcc

VOH Output High Voltage Level IOH = –5.0 mA (5V) 2.4 — V

IOH = –2.0 mA (3.3V)

VOL Output Low Voltage Level IOL = 4.2 mA (5V) — 0.4 V

IOL = 2.0 mA (3.3V)

ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commerical 5V — 2 mA

3.3V — 1

Extended 5V — 3 mA

3.3V — 2

ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 5V — 1 mA

3.3V — 0.5

ICC3 Operating Current: RAS, LCAS, UCAS, -45 — 190 mA

Random Read/Write

(2,3,4)

Address Cycling, tRC = tRC (min.) -50 — 160

Average Power Supply Current -60 — 145

ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -45 — 100 mA

EDO Page Mode

(2,3,4)

Cycling tPC = tPC (min.) -50 — 90

Average Power Supply Current -60 — 80

ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -45 — 180 mA

RAS-Only

(2,3)

tRC = tRC (min.) -50 — 160

Average Power Supply Current -60 — 145

ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -45 — 180 mA

(2,3,5)

CBR

tRC = tRC (min.) -50 — 160

Average Power Supply Current -60 — 145

ICCS Self Refresh Current Self Refresh mode — — 300 µA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

6. Iccs is sampled only not 100% tested.

6 Integrated Circuit Solution Inc.

DR004-0B