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IS41C16100S
IS41LV16100S
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
Refresh Mode: 1,024 cycles /16 ms
RAS-Only, CAS-before-RAS (CBR), and Hidden
Self refresh Mode - 1,024 cycles / 128ms
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IS41C16100S)
3.3V ± 10% (IS41LV16100S)
• Byte Write and Byte Read operation via two CAS
• Industrail Temperature Range -40°C to 85°C
EY TIMING PARAMETERS
Parameter -45
Max. RAS Access Time (tRAC) 455060ns
Max. CAS Access Time (tCAC) 111315ns
Max. Column Address Access Time (tAA)222530ns
Min. EDO Page Mode Cycle Time (tPC)162025ns
Min. Read/Write Cycle Time (tRC) 77 84 104 ns
(1)
DESCRIPTION
The ICSI IS41C16100S and IS41LV16100S are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. These devices offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of upper
and lower byte, makes the IS41C16100S ideal for use in
16-, 32-bit wide data bus systems.
These features make the IS41C16100Sand IS41LV16100S
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C16100S and IS41LV16100S are packaged in a
42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.
-50 -60 Unit
Note:
1. 45 ns Only for Vcc = 3.3V.
PIN CONFIGURATIONS
50(44)-Pin TSOP II
50
GND
49
I/O15
48
I/O14
47
I/O13
46
I/O12
45
GND
44
I/O11
43
I/O10
42
I/O9
41
I/O8
40
NC
36
NC
35
LCAS
34
UCAS
33
OE
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
GND
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
VCC
VCC
RAS
VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
42-Pin SOJ
1
VCC
2
I/O0
3
I/O1
4
I/O2
5
I/O3
6
VCC
7
I/O4
8
I/O5
9
I/O6
10
I/O7
11
NC
12
NC
13
WE
14
RAS
15
NC
16
NC
17
A0
18
A1
19
A2
20
A3
21
VCC
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
Vcc Power
GND Ground
NC No Connection
Integrated Circuit Solution Inc. 1
DR004-0B
Page 2
IS41C16100S
IS41LV16100S
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
RAS
A0-A9
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
WE
CAS WE
RAS
CONTROL
LOGICS
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
OE
CONTROL
LOGIC
OE
I/O0-I/O15
DATA I/O BUFFERS
2 Integrated Circuit Solution Inc.
DR004-0B
Page 3
IS41C16100S
IS41LV16100S
TRUTH TABLE
Function
RASRAS
RAS
RASRAS
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Read-Write
EDO Page-Mode Read
(1,2)
LLLH
(2)
1st Cycle: L H→LH→L H L ROW/COL DOUT
2nd Cycle: L H→LH→L H L NA/COL DOUT
Any Cycle: L L→HL→H H L NA/NA DOUT
EDO Page-Mode Write
(1)
1st Cycle: L H→LH→L L X ROW/COL DIN
2nd Cycle: L H→LH→L L X NA/COL DIN
EDO Page-Mode
(1,2)
1st Cycle: L H→LH→LH→LL→H ROW/COL DOUT, DIN
Read-Write 2nd Cycle: L H→LH→LH→LL→H NA/COL DOUT, DIN
Write
(2)
L→H→L L L H L ROW/COL DOUT
(1,3)
L→H→L L L L X ROW/COL DOUT
Hidden Refresh Read
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
(4)
H→L L L X X X High-Z
LCASLCAS
LCAS
LCASLCAS
UCASUCAS
UCAS
UCASUCAS
WEWE
WE
WEWE
OEOE
OE Address tR/tC I/O
OEOE
Upper Byte, High-Z
Upper Byte, DOUT
Upper Byte, High-Z
Upper Byte, DIN
→
LL→H ROW/COL DOUT, DIN
Integrated Circuit Solution Inc. 3
DR004-0B
Page 4
IS41C16100S
IS41LV16100S
Functional Description
The IS41C16100S and IS41LV16100S is a CMOS DRAM
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 16 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter ten bits.
The IS41C16100S and IS41LV16100S has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16100S and IS41LV16100S CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16100S and IS41LV16100S both
BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the resumption of normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
4 Integrated Circuit Solution Inc.
DR004-0B
Page 5
IS41C16100S
IS41LV16100S
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
V
T Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
CC Supply Voltage 5V –1.0 to +7.0 V
V
3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70 °C
Industrial Operationg Temperature –40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TA Commercial Ambient Temperature 0 — 70 °C
Industrial Ambient Temperature –40 — 85 °C
CAPACITANCE
(1,2)
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
Integrated Circuit Solution Inc. 5
DR004-0B
Page 6
IS41C16100S
IS41LV16100S
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
I
IL Input Leakage Current Any input 0V < VIN < Vcc –5 5 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –5 5 µA
0V < VOUT < Vcc
VOH Output High Voltage Level IOH = –5.0 mA (5V) 2.4 — V
IOH = –2.0 mA (3.3V)
VOL Output Low Voltage Level IOL = 4.2 mA (5V) — 0.4 V
IOL = 2.0 mA (3.3V)
ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commerical 5V — 2 mA
3.3V — 1
Extended 5V — 3 mA
3.3V — 2
ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 5V — 1 mA
3.3V — 0.5
ICC3 Operating Current: RAS, LCAS, UCAS, -45 — 190 mA
Random Read/Write
(2,3,4)
Address Cycling, tRC = tRC (min.) -50 — 160
Average Power Supply Current -60 — 145
ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -45 — 100 mA
EDO Page Mode
(2,3,4)
Cycling tPC = tPC (min.) -50 — 90
Average Power Supply Current -60 — 80
ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -45 — 180 mA
RAS-Only
(2,3)
tRC = tRC (min.) -50 — 160
Average Power Supply Current -60 — 145
ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -45 — 180 mA
(2,3,5)
CBR
tRC = tRC (min.) -50 — 160
Average Power Supply Current -60 — 145
ICCS Self Refresh Current Self Refresh mode — — 300 µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6. Iccs is sampled only not 100% tested.
6 Integrated Circuit Solution Inc.
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Page 7
IS41C16100S
IS41LV16100S
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-45 -50 -60
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 77 — 84 — 104 — ns
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column-Address
(6, 7)
(6, 8, 15)
—45—50—60 ns
—11—13—15 ns
(6)
—22—25—30 ns
tRAS RAS Pulse Width 45 10K 50 10K 60 10K ns
tRP RAS Precharge Time 28 — 30 — 40 — ns
(21)
(26)
(9, 25)
(10, 20)
7 10K 8 10K 10 10K ns
7—9—9—ns
35 — 38 — 40 — ns
10 34 12 37 14 45 ns
tCAS CAS Pulse Width
tCP CAS Precharge Time
tCSH CAS Hold Time
tRCD RAS to CAS Delay Time
tASR Row-Address Setup Time 0 — 0 — 0 — ns
tRAH Row-Address Hold Time 6 — 8 — 10 — ns
(20)
(20)
0—0—0—ns
6—8—10—ns
tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 30 — 30 — 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time
(11)
8 2310251230 ns
tRAL Column-Address to RAS Lead Time 23 — 25 — 30 — ns
tRPC RAS to CAS Precharge Time 5 — 5 — 5 — ns
tRSH RAS Hold Time
(27)
6—8—10—ns
tRHCP RAS Hold Time from CAS Precharge 37 — 37 — 37 — ns
tCLZ CAS to Output in Low-Z
tCRP CAS to RAS Precharge Time
tOD Output Disable Time
tOE Output Enable Time
(15, 29)
(19, 28, 29)
(15, 16)
(21)
0—0—0—ns
5—5—5—ns
313315315ns
—11—13—15 ns
tOED Output Enable Data Delay (Write) 20 — 20 — 20 — ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — 5 — ns
tOEP OE HIGH Pulse Width 10 — 10 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — 5 — ns
tRCS Read Command Setup Time
(17, 20)
0—0—0—ns
tRRH Read Command Hold Time 0 — 0 — 0 — ns
(referenced to RAS)
(12)
tRCH Read Command Hold Time 0 — 0 — 0 — ns
(referenced to CAS)
tWCH Write Command Hold Time
(12, 17, 21)
(17, 27)
6—8—10—ns
tWCR Write Command Hold Time 40 — 40 — 50 — ns
(referenced to RAS)
tWP Write Command Pulse Width
(17)
(17)
6—8—10—ns
tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — 10 — ns
tRWL Write Command to RAS Lead Time
tCWL Write Command to CAS Lead Time
tWCS Write Command Setup Time
(14, 17, 20)
(17)
(17, 21)
11 — 13 — 15 — ns
6—8—10—ns
0—0—0—ns
tDHR Data-in Hold Time (referenced to RAS)39—39—39—ns
Integrated Circuit Solution Inc. 7
DR004-0B
Page 8
IS41C16100S
IS41LV16100S
AC CHARACTERISTICS (Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-45 -50 -60
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tACH Column-Address Setup Time to CAS 15 — 15 — 15 — ns
Precharge during WRITE Cycle
OEH OE Hold Time from WE during 6 — 8 — 10 — ns
t
READ-MODIFY-WRITE cycle
tDS Data-In Setup Time
tDH Data-In Hold Time
(15, 22)
(15, 22)
(18)
0—0—0—ns
6—8—10—ns
tRWC READ-MODIFY-WRITE Cycle Time 95 — 108 — 133 — ns
t
RWD RAS to WE Delay Time during 55 — 64 — 77 — ns
READ-MODIFY-WRITE Cycle
tCWD CAS to WE Delay Time
tAWD Column-Address to WE Delay Time
(14, 20)
(14)
(14)
21 — 26 — 32 — ns
32 — 39 — 47 — ns
tPC EDO Page Mode READ or WRITE 16 — 20 — 25 — ns
Cycle Time
(24)
tRASP RAS Pulse Width in EDO Page Mode 45 100K 50 100K 60 100K ns
tCPA Access Time from CAS Precharge
(15)
—27—30—35ns
tPRWC EDO Page Mode READ-WRITE 51 — 56 — 68 — ns
Cycle Time
(24)
tCOH Data Output Hold after CAS LOW 5—5—5—ns
tOFF Output Buffer Turn-Off Delay from 1.6 11 1.6 12 1.6 15 ns
CAS or RAS
(13,15,19, 29)
tWHZ Output Disable Delay from WE 310310310ns
tCLCH Last CAS going LOW to First CAS 8—10—10—ns
returning HIGH
tCSR CAS Setup Time (CBR REFRESH)
tCHR CAS Hold Time (CBR REFRESH)
(23)
(30, 20)
(30, 21)
5—5—5—ns
8—8—10—ns
tORD OE Setup Time prior to RAS during 0 — 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period (1,024 Cycles) — 16 — 16 — 16 ms
tREF Self Refresh Period (1,024 Cycles) — 128 — 128 — 128 ms
tT Transition Time (Rise or Fall)
(2, 3)
150150150ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
8 Integrated Circuit Solution Inc.
DR004-0B
Page 9
IS41C16100S
IS41LV16100S
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
2. V
IH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
in a monotonic manner.
4. If CAS and RAS = V
5. If CAS = V
IL, data output may contain data from the last valid READ cycle.
IH, data output is High-Z.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
by the amount that t
8. Assumes that t
RCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
RCD exceeds the value shown.
RCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for t
10. Operation with the t
RCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
CP.
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the t
RAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either t
13. t
14. t
RCH or tRRH must be satisfied for a READ cycle.
OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
WCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to V
IH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after t
19. The I/Os are in open during READ cycles once t
OEH is met.
OD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
REF refresh requirement is exceeded.
IH and VIL (or between VIL and VIH)
Integrated Circuit Solution Inc. 9
DR004-0B
Page 10
IS41C16100S
IS41LV16100S
READ CYCLE
RAS
UCAS/LCAS
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
t
RC
t
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
RRH
t
RP
ADDRESS
Row Column Row
t
RCS
WE
t
RAC
I/O
Open Open
OE
Note:
OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
1. t
t
t
CAC
t
CLC
AA
t
RCH
(1)
t
OFF
Valid Data
t
OE
t
OES
t
OD
Undefined
Don’t Care
10 Integrated Circuit Solution Inc.
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IS41C16100S
IS41LV16100S
EARLY WRITE CYCLE (OE = DON'T CARE)
RAS
t
UCAS/LCAS
CRP
t
ASR
t
t
RAD
RAH
t
RCD
t
ASC
t
RC
t
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
ACH
t
RP
ADDRESS
WE
I/O
Row Column Row
t
CWL
t
RWL
t
WCR
t
t
WP
t
DH
WCH
t
WCS
t
DHR
t
DS
Valid Data
Don’t Care
Integrated Circuit Solution Inc. 11
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IS41C16100S
IS41LV16100S
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RWC
t
RAS
RAS
t
CSH
t
t
CAS
UCAS/LCAS
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
t
AR
t
CAH
RSH
t
RAL
t
ACH
t
CLCH
t
RP
ADDRESS
WE
I/O
OE
Row Column Row
t
RWD
t
t
RCS
t
AA
t
RAC
t
CAC
t
CLZ
Open Open
t
OE
CWD
t
AWD
Valid D
t
OD
t
OUT
DS
Valid D
t
CWL
t
RWL
t
WP
t
DH
IN
t
OEH
Undefined
Don’t Care
12 Integrated Circuit Solution Inc.
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IS41C16100S
IS41LV16100S
EDO-PAGE-MODE READ CYCLE
RAS
t
UCAS/LCAS
CRP
t
ASR
t
RAD
t
RCD
t
ASC
t
AR
t
CSH
t
CAS,
t
CLCH
t
CAH
t
ASC
t
t
CP
RASP
t
RP
(1)
t
PC
t
CAS,
t
CLCH
t
CAH
t
ASC
t
CP
t
CAS,
t
CLCH
t
RAL
t
CAH
t
RSH
t
CP
ADDRESS
Row Row
t
RAH
Column Column
t
RCS
Column
t
RCH
t
RRH
WE
t
I/O
AA
t
RAC
t
CAC
t
CLZ
Open Open
t
OE
t
OES
t
t
Valid Data
CAC
COH
t
AA
t
CPA
t
OEHC
t
CAC
t
CLZ
Valid Data
t
OD
t
AA
t
CPA
t
OES
Valid Data
t
OE
t
OFF
t
OD
OE
t
OEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the t
PC specifications.
Integrated Circuit Solution Inc. 13
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IS41C16100S
IS41LV16100S
EDO-PAGE-MODE EARLY-WRITE CYCLE
RAS
t
CSH
t
UCAS/LCAS
CRP
t
ASR
t
RAD
t
RCD
t
ASC
t
AR
t
ACH
t
CAS,
t
CLCH
t
CAH
t
ASC
t
t
CP
RASP
t
t
RP
CP
t
RHCP
t
PC
t
CAS,
t
CLCH
t
ACH
t
CAH
t
ASC
t
CP
t
t
t
ACH
t
RAL
t
RSH
CAS,
CLCH
t
CAH
ADDRESS
WE
I/O
OE
Row Row
t
RAH
Column Column
t
CWL
t
WCS
t
WCH
t
WP
t
WCR
t
DHR
t
DS
t
DH
Valid Data
t
DS
Column
t
CWL
t
WCS
t
WCH
t
WP
t
DH
Valid Data
t
DS
t
WCH
t
DH
Valid Data
t
CWL
t
WCS
t
WP
t
RWL
Don’t Care
14 Integrated Circuit Solution Inc.
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IS41C16100S
IS41LV16100S
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
t
RASP
RAS
/ t
t
AWD
PRWC
t
t
CAH
t
CWD
D
(1)
CAS, tCLCH
t
CWL
t
WP
t
DH
t
DS
OUT
t
RSH
t
t
CP
t
ASC
t
CPA
t
CAC
t
CLZ
D
IN
t
OD
t
OE
CAS, tCLCH
t
RAL
t
CAH
t
RWL
t
CWL
t
WP
t
AWD
t
CWD
t
AA
t
DH
t
DS
D
OUT
t
IN
OD
t
OEH
D
UCAS/LCAS
ADDRESS
WE
I/O
OE
t
t
t
CAC
t
CLZ
CP
t
t
CPA
t
OE
PC
Column
AA
t
RWD
RCS
t
t
RCD
ASC
CSH
t
CAS, tCLCH
t
AR
t
CAH
t
ASC
Column Column
t
CWL
t
WP
t
AWD
t
CWD
t
t
RAC
t
CAC
t
CLZ
t
AA
OE
t
DH
t
DS
D
OUT
IN
t
OD
D
t
CRP
t
ASR
t
RAH
t
RAD
Row Row
t
t
Open Open
t
RP
t
CP
Undefined
Don’t Care
Note:
PC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
1. t
measurements must meet the t
PC specifications.
Integrated Circuit Solution Inc. 15
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Page 16
IS41C16100S
IS41LV16100S
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
RAS
t
CSH
t
t
CAS
t
CAH
t
RCH
t
Valid Data (B)
PC
WHZ
t
ASC
t
t
CP
t
WCS
DS
t
RSH
t
CAS
t
ACH
t
RAL
t
CAH
t
WCH
t
DH
D
IN
UCAS/LCAS
ADDRESS
WE
I/O
OE
t
t
CAH
t
CAS
PC
t
CP
t
ASC
t
Valid Data (A)
Column (B)
t
AA
t
CPA
t
CAC
COH
t
CRP
t
ASR
t
RAH
Row Row
t
RAD
t
RCD
t
AR
t
ASC
Column (A) Column (N)
t
RCS
t
AA
t
RAC
t
CAC
Open Open
t
OE
t
RP
t
CP
Don’t Care
16 Integrated Circuit Solution Inc.
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IS41C16100S
IS41LV16100S
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
t
CSH
t
UCAS/LCAS
ADDRESS
WE
I/O
OE
CRP
t
ASR
t
RAH
Row Row
t
RAD
t
RCD
t
AR
t
ASC
Column (A) Column (N)
t
RCS
t
AA
t
RAC
t
CAC
Open Open
t
OE
t
CAH
t
CAS
t
PC
t
t
ASC
Valid Data (A)
t
RASP
CP
Column (B)
t
CPA
t
CAC
t
COH
t
RP
t
PC
t
CAS
t
CAH
t
RCH
t
AA
t
Valid Data (B)
WHZ
t
ASC
t
t
CP
t
DS
WCS
DIN
t
WCH
t
t
CAH
ACH
t
t
DH
t
RAL
t
CAS
RSH
t
CP
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
RASRAS
t
RAS
RAS
t
CRP
UCAS/LCAS
t
RAH
ADDRESS
t
ASR
Row Row
I/O
Open
Undefined
Don’t Care
t
RC
t
RP
t
RPC
Don’t Care
Integrated Circuit Solution Inc. 17
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IS41C16100S
IS41LV16100S
CBRCBR
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
CBRCBR
t
t
CSR
RAS
t
RPC
RAS
UCAS/LCAS
t
RPC
t
CP
t
RP
t
CHR
t
t
RP
t
CSR
RAS
t
CHR
I/O
HIDDEN REFRESH CYCLE
RAS
t
CRP
UCAS/LCAS
t
ASR
ADDRESS
I/O
(1)
(WE = HIGH; OE = LOW)
t
RAS
t
RCD
t
AR
t
RAD
t
RAH
t
ASC
t
RAL
Row Column
t
RAC
t
CLZ
Open Open
t
OE
t
AA
Open
t
CAC
t
CAH
t
RSH
t
ORD
t
t
RP
RAS
t
CHR
t
OFF
(2)
Valid Data
t
OD
OE
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
2. t
18 Integrated Circuit Solution Inc.
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IS41C16100S
IS41LV16100S
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
t
CSR
RASS
t
RPC
t
CP
Open
t
RPS
t
RP
V
DQ
IH
V
IL
t
t
RPC
t
CP
V
IH
V
IL
V
OH
V
OL
CHD
RAS
UCAS/LCAS
TIMING PARAMETERS
-45 -50 -60
Symbol Min. Max. Min. Max. Min. Max. Units
Don’t Care
tCHD 8— 8— 10— ns
tCP 7— 9— 9— ns
tCSR 5— 5— 5— ns
tRASS 100 — 100 — 100 — µs
tRP 28 — 30 — 40 — ns
tRPS 77 — 84 — 104 — ns
tRPC 5— 5— 5— ns
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
45 IS41C16100S-45K 400mil SOJ
IS41C16100S-45T 400mil TSOP-2
50 IS41C16100S-50K 400mil SOJ
IS41C16100S-50T 400mil TSOP-2
60 IS41C16100S-60K 400mil SOJ
IS41C16100S-60T 400mil TSOP-2
ORDERING INFORMATION: 5V
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No. Package
45 IS41C16100S-45KI 400mil SOJ
IS41C16100S-45TI 400mil TSOP-2
50 IS41C16100S-50KI 400mil SOJ
IS41C16100S-50TI 400mil TSOP-2
60 IS41C16100S-60KI 400mil SOJ
IS41C16100S-60TI 400mil TSOP-2
Integrated Circuit Solution Inc. 19
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IS41C16100S
IS41LV16100S
ORDERING INFORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
45 IS41LV16100S-45K 400mil SOJ
IS41LV16100S-45T 400mil TSOP-2
50 IS41LV16100S-50K 400mil SOJ
IS41LV16100S-50T 400mil TSOP-2
60 IS41LV16100S-60K 400mil SOJ
IS41LV16100S-60T 400mil TSOP-2
ORDERING INFORMATION: 3.3V
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No. Package
45 IS41LV16100S-45KI 400mil SOJ
IS41LV16100S-45TI 400mil TSOP-2
50 IS41LV16100S-50KI 400mil SOJ
IS41LV16100S-50TI 400mil TSOP-2
60 IS41LV16100S-60KI 400mil SOJ
IS41LV16100S-60TI 400mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
20 Integrated Circuit Solution Inc.
DR004-0B
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