ICSI ICS95V847 User Manual
查询ICS95V847YGLF-T供应商
Integrated
ICS95V847
Circuit
Systems, Inc.
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• Zero Delay Board Fan Out, SO-DIMM
• Provides complete DDR registered DIMM solution
with ICSSSTV16857, ICSSSTV16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 5 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• CYCLE - CYCLE jitter: <60ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±30ps
• DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
GND
CLKC0
CLKT0
GND
VDD
CLK_INT
CLK_INC
AVD D
AGND
CLKC1
CLKT1
VDD
4.40 mm. Body, 0.65 mm. pitch
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
847
19
18
17
ICS95V
16
15
14
13
24-Pin TSSOP
CLKT4
CLKC4
CLKC3
CLKT3
VDD
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
GND
Functionality
STUPNISTUPTUO
DDVATNI_KLCCNI_KLCTKLCCKLCTTUO_BFCTUO_BF
DNGL HLHL H ffo/dessapyB
DNGH LHLH L ffo/dessapyB
V5.2
LHLHLH no
)mon(
V5.2
HLHLHL no
)mon
(
0718D—04/08/05
Block Diagram
etatSLLP
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
ICS95V847
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
02,21,5DDVRWPV5.2,ylppusrewoP
31,4,1DNGRWPdnuorG
8DDVARWPV5.2,ylppusrewopgolanA
9DNGARW
42,12,51,11,3]4:0[TKLCTUOstuptuoriaplaitnereffidfokcolC"eurT"
PdnuorggolanA
32,22,41,01,2]4:0[CKLCTUOstuptuori
6TNI_KLCNItupnikcolcecnerefer"eurT"
7CNI_KLCNItupnikcolcecnerefer"yratn
61TTUO_BFTUO
71CTUO_BFTUO
91TNI_BFNI
81CNI_BFNI
emelpmoC"
TNI_BF
pmoC"
CNI_BFot
aplaitnereffidfoskcolc"yratnemelpmoC"
sehctiwstI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF""eurT"
hT.KLCehtsaycneuqerfemasehtta
skcabdeefsedivorp,tupnikcabdeeF"eurT"
rorreesahpetanimileotTNI_KLChtiwnoitazinorhcnys
otderiwebtsumtuptuosi
tI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF"yratnemel
deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws
rofLLPlanretniehtotlangi
niehtotlangissedivorp,tupnikcabdeeF"yratnemelpmoC"
rorreesahpetanimileotCNI_KLChtiwnoitazinorhcnysrof
LLPlanret
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The
clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog
power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS95V847 is characterized for operation from 0°C to 85°C.
0718D—04/08/05
2
Absolute Maximum Ratings
p
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDD + 0.5V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
ICS95V847
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage A
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current I
Input Low Current I
Operating Supply
Current
I
DD2. 5
I
High Impedance
ut Current
Out
Input Clamp Voltage V
High-level output
voltage
V
Low-level output voltage V
Input Capacitance
1
Guaranteed by design at 233MHz, not 100% tested in production.
1
IH
IL
DDPD
I
OZ
IK
OH
OL
C
IN
, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
VDD
VI = VDD or GND 5 µA
VI = VDD or GND 5 µA
CL = 0pf @ 200MHz 148 mA
CL = 0pf 100 µA
V
= 2.7V, Vout = VDD or
DD
GND
±10 mA
VDD = 2.3V Iin = -18mA -1.2
= -1 mA VDD - 0.1 V
I
OH
I
= -12 mA 1.7V V
OH
I
=1 mA 0.1 V
OL
I
=12 mA 0.6 V
OH
VI = GND or V
DD
2.5 3.5 pF
V
0718D—04/08/05
3
Loading...