ICSI ICS94229 User Manual

VDDREF

GND

X1
X2

AVDD48

*FS2/48MHz

*FS3/24_48MHz

GND

*WDEN/PCICLK_F

*SEL24_48#/PCICLK0

PCICLK1

GND
PCICLK2
PCICLK3

VDDPCI
PCICLK4
PCICLK5
PCICLK6

GND
PCICLK7
PCILCK8

PCICLK9_E

VDDPCI

SRESET#

REF0/
REF1/FS1*
REF_F
RATIO
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
S DATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP

FS0*

ICS94229

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

查询ICS94229供应商

Integrated

ICS94229

Circuit
Systems, Inc.

Advance Information

Programmable System Clock Chip for AMD - K7™ processor

Recommended Application:

VIA KT266 style chipset

Output Features:

• 1 - Differential pair open drain CPU clocks @ 2.5V

• 1 - Differential pair push-pull CPU clocks @ 2.5V

• 11 - PCI including 1 free running and 1 early @ 3.3V

• 1 - 48MHz, @ 3.3V fixed

• 1 - 24/48MHz @ 3.3V

• 3 - REF @ 3.3V, 14.318MHz.

Features:

• Programmable output frequency.

• Programmable output rise/fall time.

• Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.

• Real time system reset output.

• Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage.

• Watchdog timer technology to reset system
if over-clocking causes malfunction.

• Uses external 14.318MHz crystal.

Skew Specifications:

• CPU - CPU: <175ps

• PCI - PCI: <500ps

• CPU (early - PCI: min=1.0ns, max=2.0ns

• CPU cycle to cycle jitter: <250ps

* Internal Pull-up Resistor of 120K to VDD

Pin Configuration

48-Pin 300mil SSOP

Block Diagram

SEL24_48#

PCI_STOP#

CPU_STOP#

AGP_STOP#

94229 Rev - 05/31/01

Third party brands and names are the property of their respective owners.

X2

S DATA

SCLK

FS (3:0)

PD#

Functionality

PLL2

/ 2

X1

XTAL

OSC

PLL1

Spread

Spectrum

Control

Logic

Config.

Reg.

CPU

DIVDER

CPU

DIVDER

PCI

DIVDER

AGP

DIVDER

Stop

Stop

Stop

Stop

48MHz (1:0)

2

24_48MHz

REF (1:0)

2

REF_F

CPUCLKT0
CPUCLKC0

CPUCLK_CST0
CPUCLK_CSC0

PCICLK9_E

PCICLK (8:0)

9

PCICLK_F

AGP (2:0)

3

SRESET#

RATIO

3SF2SF1SF0SF

0000 33.33287.7788.83
0001 00.02233.3776.63
0010 00.01200.0700.53
0011 00.00276.6633.33
0100 00.09100.6700.83
0101 00.08100.2700.63
0110 00.07100.8600.43
0111 00.05100.5705.73
1000 00.04100.0700.53
100 1 00.02100.0600.03
1010 00.01100.6600.33
1011 76.6676.6633.33
1100 00.00276.6633.33
1101 76.66176.6633.33
1110 00.00176.6633.33
1111 33.33176.6633.33

ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.

UPC

)zHM(

PGA

)zHM(

KLCICP
)zHM(

ICS94229

Advance Information

Pin Descriptions

REBMUNNIPEMANNIPEPYTNOITPIRCSED

,52,32,51,1DDVRWPV3.3lanimon,ylppusrewoP

,91,21,8,2

34,73,92
31XNI 2Xmorfrotsiserkcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
42XTUO)Fp63(pacdaollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
584DDVARWPV3.3lanimon,ylppusrewoP

6

7

9

01

11,31,41,61
22E_9KLCICPTUO .#POTS_ICPybdeppotsebnaC.sn2ybskcolcICPlarenegsdaeL.kcolcICPylraE
42#TESERS

62,72,82)0:2(PGATUOstuptuokcolcPGA
03KLCSNIIfotupnikcolC
13ATADSO/IIrofnipataD
23DNGARWPdnuorggolanA
33DDVARWPV3.3lanimon,ylppusrewoP

43#DPNI

53#POTS_ICPNI woltupninehw,level0cigoltaskcolcF_KLCICPehtsedisebsKLCICPllaspotS
63#POTS_UPC

830CSC_KLCUPCTUO

930TSC_KLCUPCTUO
04LDDVRWPV5.2lanimon,sKLCUPCrofylppusrewoP
240TKLCUPCTUO

140CKLCUPCTUO
44#POTS_PGANIwoltupninehw,level0cigoltaskcolcPGAllaspotS

54
64F_FERTUO#POTS_FERybdetcetffaton,.kcolcecnerefergninnureerfzHM813.41

74

84

DNGRWPdnuorG

2,1

2SF

zHM84TUOkcolctuptuozHM84

2,1

3SF

zHM84_42TUOtuptuokcolczHM84ro42

NEDWNI .zHM001siycneuqerfefastluafeD.tiucricgodhctawfoelbaneerawdraH

F_KLCICPTUO .tnemeganamrewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

#84_42LES

0KLCICPTUOtuptuokcolcICP

,71,81,02,12

1

OITARTUOegdirBhtuoSehtotzHM331rof"1"rozHM001rof"0"astuptuO

2,1

1SF

1FERTUO.kcolcecnereferzHM813.41

2,1

0SF

0FERTUO.kcolcecnereferzHM813.41

2,1

)1:8(KLCICPTUO.stuptuokcolcICP

2,1

NItupnIdehctaL.niptcelesycneuqerF

NItupnIdehctaL.niptcelesycneuqerF

NItuptuo7niprofzHM84ro42tcelesottupnicigoL

TUO .wolevitcasilangissihT.tuoemitremtgodhctawroflangistesermetsysemitlaeR

NI

NItupnIdehctaL.niptcelesycneuqerF

NItupnIdehctaL.niptcelesycneuqerF

2

2

tupnitnarelotV5,tupniC

tnarelotV5yrtiucricC

rewopwolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
ehT.deppotseralatsyrcehtdnaOCVehtdnadelbasideraskcolclanretniehT.etats

.sm3nahtretaergebtonlliwnwodrewopehtfoycnetal

"0"cigoltaskcolcSC_CKLCUC&CKLCUPC,TKLCUPCstlahtupnisuonorhcnysasihT

.wolnevirdnehwlevel

nadeenstuptuollup-hsupesehT.tuptuoUPCriaplaitnereffidfokcolc"yratnemelpmoC"

)llup-hsup(pu-llupV5.1lanretxe

V5.1lanretxenadeenstuptuollup-hsupesehT.tuptuoUPCriaplaitnereffidfokcolc"eurT"

.)llup-hsup(pu-llup

V5.1lanretxenadeenstuptuoniardnepoesehT.tuptuoUPCriaplaitnereffidfokcolc"eurT"

.)niardnepo(pu-llup

nadeenstuptuoniardnepoesehT.tuptuoUPCriaplaitnereffidfokcolc"yratnemelpmoC"

.)niardnepo(pu-llupV5.1lanretxe

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

Third party brands and names are the property of their respective owners.

2

ICS94229

Advance Information

General Description

The ICS94229 is a main clock synthesizer chip for AMD-K7 based systems with VIA KT266 style chipset. This provides all
clocks required for such a system.

The ICS94229 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks.
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clocking.

SRESET# Signal Description

The SRESET# signal from ICS94229 system clock generator is a real time active low pulse that can be used to reset the system.
The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated,

the SRESET# output will be driven to a low with a 288ms pulse width.

Third party brands and names are the property of their respective owners.

3

ICS94229

Advance Information

General I2C serial interface information

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending Byte 0 through Byte 16

(see Note 2)

• ICS clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Write:

Controll e r (Host)

Start Bit

Address D2

Dummy Command Code

Dummy Byte Count

(H)

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

ICS (Slave/Receiver)

(H)

ACK

ACK

ACK

ACK

ACK

ACK

ACK

ACK

ACK

ACK

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• ICS clock sends Byte 0 through byte 6 (default)

• ICS clock sends Byte 0 through byte X (if X

written to byte 6).

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

H ow to Read:

Controlle r (Host)

Start B it

Addres s D3

ACK

ACK

ACK

ACK

ACK

ACK

ACK

ACK

If 7

has been wri t ten to B 6

H

ACK

(H)

ICS (Slave/Receiver)

ACK

Byte Count

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

(H)

(H)

was

Byte 14

ACK

Byte 15

ACK

Byte 16

ACK

Stop Bit

*See notes on the following page.

Third party brands and names are the property of their respective owners.

If 1A

has been wri t ten to B 6

H

ACK

If 1B

has been wri t ten to B 6

H

ACK

has been wri t ten to B 6

If 1C

H

ACK

St op Bit

Byte 14

Byte 15

Byte 16

4

Advance Information

g

Brief I2C registers description for

Programmable System Frequency Generator

Register Name Byte Description PWD Default

Functionality & F requency
Select Register

Output Control Registers 1, 2, 3

Vendor ID & Revision ID
Registers

Byte Count
Read B ack Register

Watchdog Enable Register 4

Watchdog Control Registers

VCO Con trol Selectio n Bit 4, 5

VCO Frequency Control
Registers

Spread Spectrum Control
Registers

Group Skews Control
Registers

Output Rise/Fall Time
Select Registers

0

5, 6, 7

8

9, 10

11, 12

13, 14

15, 16

Output frequency, hardware / I
frequency s elect, spread spectrum &
output enable control register.

Active / inactive outpu t control
registers/latch inputs read back.

Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.

Writing to this regis ter w ill con figu re
byte count and how many b yte w ill be

read back. Do not write 00

Writing to this regis ter w ill con figu re the
number of seconds for the watchdog
timer to res et.

Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
confi

ured in th is register .

This bit s elect w hether the outp ut
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.

Thes e registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.

Thes e registers control the spread
percentage amount.

Increment or d ecrement the group skew
amount as compared to the initial skew.

These registers will control the output
ris e and fall time.

2

C

to this byte.

H

See individual
byte description

See individual
byte description

See individual
byte description

000,0000

Depended on
hardware/byte 0
con figuration

Depended on
hardware/byte 0
con figuration

See individual
byte description

See individual
byte description

ICS94229

08

H

10

H

0

Notes:

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is

defined by writing to byte 8.

2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written

but not 15, neither byte 14 or 15 will load into the receiver.

3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

4. The input is operating at 3.3V logic levels.

5. The data byte format is 8 bit bytes.

6. To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.

7. At power-on, all registers are set to a default condition, as shown.

Third party brands and names are the property of their respective owners.

2

C interface, the protocol is set to use only Block-Writes from the controller. The

5

ICS94229

Advance Information

Serial Configuration Command Bitmap

Byte0: Functionality and Frequency Select Register (default = 0)

Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SSB1 SSB0 FS3 FS2 FS1 FS0

0 0 0 0 0 0 233.33 77. 78 38.88 +/- 0. 25% Cent er Spread N/ A
0 0 0 0 0 1 220.00 73. 33 36.67 +/- 0. 25% Cent er Spread N/ A
0 0 0 0 1 0 210.00 70. 00 35.00 +/- 0. 25% Cent er Spread N/ A
0 0 0 0 1 1 200.00 66. 67 33.33 +/- 0. 25% Cent er Spread N/ A
0 0 0 1 0 0 190.00 76. 00 38.00 +/- 0. 25% Cent er Spread N/ A
0 0 0 1 0 1 180.00 72. 00 36.00 +/- 0. 25% Cent er Spread N/ A
0 0 0 1 1 0 170.00 68. 00 34.00 +/- 0. 25% Cent er Spread N/ A
0 0 0 1 1 1 150.00 75. 00 37.50 +/- 0. 25% Cent er Spread N/ A
0 0 1 0 0 0 140.00 70. 00 35.00 +/- 0. 25% Cent er Spread N/ A
0 0 1 0 0 1 120.00 60. 00 30.00 +/- 0. 25% Cent er Spread N/ A
0 0 1 0 1 0 110.00 66. 00 33.00 +/- 0. 25% Cent er Spread N/ A
0 0 1 0 1 1 66.67 66.67 33. 33 +/- 0.25% Center S pread N/A
0 0 1 1 0 0 200.00 66. 67 33.33 +/- 0. 25% Cent er Spread N/ A
0 0 1 1 0 1 166.67 66. 67 33.33 +/- 0. 25% Cent er Spread N/ A
0 0 1 1 1 0 100.00 66. 67 33.33 +/- 0. 25% Cent er Spread 0
0 0 1 1 1 1 133.33 66. 67 33.33 +/- 0. 25% Cent er Spread 1
1 0 0 0 0 0 200.00 66. 67 33.33 0 to -0.5% Down S pread N/A
1 0 0 0 0 1 166.67 66. 67 33.33 0 to -0.5% Down S pread N/A
1 0 0 0 1 0 100.00 66. 67 33.33 0 to -0.5% Down S pread 0
1 0 0 0 1 1 133.33 66. 67 33.33 0 to -0.5% Down S pread 1
1 0 0 1 0 0 200.00 66. 67 33.33 +/- 0. 50% Cent er Spread N/ A
1 0 0 1 0 1 166.67 66. 67 33.33 +/- 0. 50% Cent er Spread N/ A
1 0 0 1 1 0 100.00 66. 67 33.33 +/- 0. 50% Cent er Spread 0
1 0 0 1 1 1 133.33 66. 67 33.33 +/- 0. 50% Cent er Spread 1
1 1 1 0 0 0 200.00 66. 67 33.33 +/- 0. 75% Cent er Spread N/ A
1 1 1 0 0 1 166.67 66. 67 33.33 +/- 0. 75% Cent er Spread N/ A
1 1 1 0 1 0 100.00 66. 67 33.33 +/- 0. 75% Cent er Spread 0
1 1 1 0 1 1 133.33 66. 67 33.33 +/- 0. 75% Cent er Spread 1
1 1 1 1 0 0 200.00 66. 67 33.33 0 to + 0.5% Up S pread N/A
1 1 1 1 0 1 166.67 66. 67 33.33 0 to + 0.5% Up S pread N/A
1 1 1 1 1 0 100.00 66. 67 33.33 0 to + 0.5% Up S pread 0
1 1 1 1 1 1 133.33 66. 67 33.33 0 to + 0.5% Up S pread 1

Bit 6: 0 = Hardware select; 1 = I
Bit 7: 0 = Spread off; 1 = S pread s pec t rum enable. Default is O FF

CPUCL K AGP CLK PCI CLK S p re ad P erce n ta ge

2

C select. Default is OFF.

RATIO

Third party brands and names are the property of their respective owners.

6