Integrated
Circuit
ICS9248-98
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
440BX/VIA Apollo 133 style chipset.
Output Features:
• 2 - CPUs @2.5V, up to 166MHz.
• 1 - IOAPIC @ 2.5V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management: PCI, CPU stop and Mode
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: <250ps
• PCI – PCI: <500ps
• BUFFER_IN-SDRAM: <5ns
• CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns
*PCI_STOP/REF0
VDD1
GND
VDD2
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Pin Configuration
1
2
X1
X2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-98
48-Pin 300mil SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL1
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL2
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*
Block Diagram
PLL2
/2
X1
X2
BUFFER IN
FS(3:0)
MODE
CLK_STOP#
PCI_STOP#
SDATA
SCLK
9248-98 Rev D 11/6/00
Third party brands and names are the property of their respective owners.
XTAL
OSC
PLL1
Spread
Spectrum
4
LATCH
4
POR
Control
Logic
Config.
Reg.
PCI
CLOCK
DIVDER
STOP
STOP
STOP
STOP
2
12
5
48MHz
24MHz
IOAPIC
REF(1:0)
CPUCLK_F
CPUCLK 1
SDRAM (11:0)
SDRAM_F
PCICLK (4:0)
PCICLKF
Functionality
3SF2SF1SF0SF
0000 00.0800.04
0001 00.5705.73
0010 13.3856.14
0011 28.6614.33
0100 00.30133.43
0101 10.21143.73
0110 10.8610.43
0111 32.00114.33
1000 00.02100.04
1001 99.41133.83
1010 99.90166.63
1011 00.50100.53
1100 00.04100.53
1101 00.05105.73
1110 00.42100.13
1111 99.23152.33
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
UPC
KLCICP
)zHM(
)zHM(
ICS92 48-98
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
11DDVRWPV3.3lanimon,ylppusrewopLATX,FER
2
,22,61,9,3
54,93,33
41XNI
52XTUO
41,62DDVRWPV3.3lanimon,KLCICPdnaF_KLCICProfylppuS
7
8
01,11,21,31)1:4(KLCICPTUO
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
,12,02,81,71
,23,13,92,82
83,73,53,43
63,03,913DDVRWP.V3.3lanimon,eroCLLPUPCdnaMARDSrofylppuS
32ATADSO/IIrofnipataD
42KLCSNIIfotupnikcolC
52
62
724DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
04F_MARDSTUO#POTS_KLCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI
242LDDVRWPlanimonV5.2skcolcUPCrofylppuS
341KLCUPCTUO
44F_KLCUPCTUO#POTS_KLCehtybdetceffatoN.kcolcUPCgninnureerF
64
74CIPAOITUOCIPAOI.1LDDVybderewoPzHM813.41.tuptuokcolc
841LDDVRWPlanimonV5.2,CIPAOIrofylppuS
0FERTUO.kcolcecnereferzhM813.41
1
#POTS_ICP
NI
DNGRWPdnuorG
F_KLCICPTUO
2,1
EDOM
NI
3SFNIDNGotnwod-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUO
)0:11(MARDSTUO
zHM42TUOkcolctuptuozHM42
2,1
1SF
NI.tupnIdehctaL.niptcelesycneuqerF
zHM84TUOkcolctuptuozHM84
2,1
0SF
NItupnIdehctaL.niptcelesycneuqerF
1FERTUO.kcolcecnereferzHM813.41
2,1
2SF
NItupnIdehctaL.niptcelesycneuqerF
woltupninehw,level0cigoltaskcolcKLCICPstlaH
)0=EDOM,edomelibomnI(
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf7niP
.tupnIdehctaL
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
.)tespihcybdellortnoc(
2
2
tnarelotV5yrtiucricC
tupnitnarelotV5,tupniC
skcolcMARDS&CIPAOI,KLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel"0"cigolta
.2LDDVybderewop,stuptuokcolcUPC
woL=#POTS_KLCfiwoL
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS92 48-98
General Description
The ICS9248-98 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.
2
Spread spectrum may be enabled through I
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-98
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
stop clock programming and frequency selection.
2
C interface allows changing functions,
C programming.
Mode Pin - Power Management Input Control
7niP,EDOM
)tupnIdehctaL(
0
1
2niP
#POTS_ICP
)tupnI(
0FER
)tuptuO(
Power Groups
VDD1 = REF, X1, X2
VDD2 = PCICLK_F, PCICLK
VDD3 = SDRAM, supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK 1, CPUCLK_F
Third party brands and names are the property of their respective owners.
3
ICS92 48-98
K
0
2
3
5
K
K
K
K
K
K
K
K
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
(H)
AC
AC
AC
AC
ACK
AC
AC
AC
AC
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
AC
Byte Count
Byte
Byte 1
Byte
Byte
Byte 4
Byte
(H)
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
4
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
tiBnoitpircseDDWP
)4,5,6,7,2(tiB
00000 00.0800.04
00001 00.5705.73
00010 13.3856.14
00011 28.6614.33
00100 00.30133.43
00101 10.21143.73
00110 10.8610.43
00111 32.00114.33
01000 00.02100.04
01001 99.41133.83
01010 99.90166.63
01011 00.50100.53
01100 00.04100.53
01101 00.05105.73
01110 00.42100.13
,2tiB
4:7tiB
01111 99.23152.33
10000 00.53157.33
10001 99.92105.23
100 10 00.62105.13
100 11 00.81133.93
10100 89.51166.83
10101 00.5976.13
10110 00.0900.03
10111 10.5843.82
11000 00.66105.14
11001 10.06100.04
11010 99.45157.83
11011 59.74199.63
11100 89.54105.63
11101 89.34199.53
11110 99.14105.53
11111 10.83105.43
3tiB
1tiB
0tiB
lamroN-0
gninnuR-0
stuptuollaetatsirT-1
KLCUPC
)zHM(
4:7,2tiBybdetcelessiycneuqerF-1
ICS92 48-98
KLCICP
)zHM(
1010,0
1etoN
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
daerpSretneC%52.0±delbanEmurtcepSdaerpS-1
0
1
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
5
ICS92 48-98
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X #2SFdehctaL
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 F_MARDS
2tiB-1 )devreseR(
1tiB341 1KLCUPC
0tiB441 F_KLCUPC
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-X #0SFdehctaL
5tiB621 zHM84
4tiB521 zHM42
3tiB-1 )devreseR(
,81,71
2tiB
1tiB
0tiB
1)8:11(MARDS
12,02
,92,82
1)4:7(MARDS
23,13
,53,43
1)0:3(MARDS
83,73
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB71 F_KLCICP
5tiB-1 )devreseR(
4tiB311 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB011 1KLCICP
0tiB81 0KLCICP
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 0CIPAOI
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 1FER
0tiB210FER
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Note: Dont write into this register, writing into this
register can cause malfunction
6
ICS92 48-98
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-98. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
IOAPIC
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-98.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-98
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
7
ICS92 48-98
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-98. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-98 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-98 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-98.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
8
Shared Pin Operation Input/Output Pins
ICS92 48-98
The I/O pins designated by (input/output) on the ICS924898 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Device
Pad
Third party brands and names are the property of their respective owners.
Via to
VDD
2K W
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
9
ICS92 48-98
1
1
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Recommended Operating Conditions
Operating Voltage, VDD Supply. . . . . . . . . . . . . . 2.5 to 3.7V
Operating Voltage, VDDL Supply . . . . . . . . . . . . 1.8 to 3.7V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD =V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
Input Low Current I
I
Operating Supply Current
DD3.3OP66CL
I
DD3.3OP100CL
Input frequency F
Input Capacitance
1
Clk Stabilization
1
Guaranteed by design, not 100% tested in production.
C
C
T
= 3.3 V +/-5% (unless otherwise stated)
DDL
IH
IL
IH
IL1
IL2
VIN=V
DD
VIN = 0 V; Inputs with no pull-up resistors -5 uA
VIN = 0 V; Inputs with pull-u p resistors -200 uA
= 0 pF; Selec t @ 66.8 MHz 94
= 0 pF; Select @ 100 MHz 130
VDD = 3.3 V 12 14.318 16 MHz
i
Logic Inputs 5 pF
IN
INX
STAB
X1 & X2 pins 27 45 pF
From VDD = 3.3 V to 1% target Freq.
DD
+0.5 V
2V
+0.3 V
DD
VSS-0.3 0.8 V
5uA
180
mA
3ms
Electrical Characteristics - Input/Supply/Common Ou tput Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
Operating Supply Current mA
Skew
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
DD2.5OP66CL
I
DD2.5OP100CL
T
CPU-PCI
= 0 pF; Select @ 66.8 MHz 12 72
= 0 pF; Select @ 100 MHz 9 100
VT =1.5 V; VTL = 1.25V
=2.5V +/- 5% (unless otherwise stated)
DDL
10
12.464 ns
ICS92 48-98
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
Output Low Voltage V
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew window
Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
1
1
1
1
1
OH2B
OL2B
I
OH2B
I
OL2B
t
r2B
t
f2B
d
t
sk2B
t
jcyc-cyc2B
=2.5V +/- 5%; CL = 20 pF (unless otherwise stated)
DDL
IOH = -8 mA 2 2.4 V
IOL = 12 mA 0.17 0.4 V
VOH = 1.7 V -58 -16
VOL = 0.7 V 19 46
VOL = 0.4 V, VOH = 2.0 V 1.08 1.6 ns
VOH = 2.0 V, VOL = 0.4 V 0.96 1.6 ns
t2B
VT = 1.25 V 45 49.4 55
VT = 1.25 V 62 175 ps
VT = 1.25 V
216 250 ps
mA
mA
%
Electrical Characteristics - PCICLK
TA = 0 - 70C; V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
Output Low Voltage V
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew window
Jitter, Absolute
1
Guaranteed by design, not 100% tested in production.
= 3.3V +/-5%, V
DD
1
1
1
1
1
I
I
t
OH1
OL1
OH1
OL1
t
r1
t
f1
d
t
sk1
jabs1
= 2.5V +/-5%; CL = 30 pF (unless otherwise stated)
DDL
IOH = -11 mA 2.4 3.15 V
IOL = 9.4 mA 0.13 0.4 V
VOH = 2.0 V -97 -40
VOL = 0.8 V 41 69
VOL = 0.4 V, VOH = 2.4 V 1.42 2.0 ns
VOH = 2.4 V, VOL = 0.4 V 1.35 2.0 ns
t1
VT = 1.5 V 45 51 55 %
VT = 1.5 V 251 500 ps
VT = 1.5 V
-500 180 500 ps
mA
mA
Third party brands and names are the property of their respective owners.
11
ICS92 48-98
1 (Buffer
Electrical Characteristics - SDRAM
TA = 0 - 70C; V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
Output Low Voltage V
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew window
Propagation Time
In to Output)
1
Guaranteed by design, not 100% tested in production.
= 3.3V +/-5%, V
DD
1
1
1
1
= 2.5V +/-5%; CL = 30 pF (unless otherwise stated)
DDL
OH3
OL3
I
OH3
I
OL3
t
r3
t
f3
d
t3
t
sk3
Tprop ns
IOH = -28 mA 2.4 3 V
IOL = 20 mA 0.18 0.4 V
VOH = 2.0 V -110 -40
VOL = 0.8 V 41 86
VOL = 0.4 V, VOH = 2.4 V 1.13 2 ns
VOH = 2.4 V, VOL = 0.4 V 1.11 2 ns
VT = 1.5 V 45 53.1 55 %
VT = 1.5 V 215 250 ps
= 1.5 V
V
T
3.26
5
mA
mA
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD=3.3V +/- 5%, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
Output Low Voltage V
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter, Absolute
1
Guaranteed by design, not 100% tested in production.
1
1
1
1
OH4B
OL4B
I
OH4B
I
OL4B
t
r4B
t
f4B
d
t4B
t
jabs4B
=2.5V +/- 5%; CL = 20 pF (unless otherwise stated)
DDL
IOH = -8 mA 2 2.4 V
IOL = 12 mA 0.17 0.4 V
VOH = 1.7 V -58 -16
VOL = 0.7 V 19 46
VOL = 0.4 V, VOH = 2.0 V 1.14 2 ns
VOH = 2.0 V, VOL = 0.4 V 1.07 2 ns
VT = 1.25 V 45 52.7 55
VT = 1.25 V
-1 0.27 1 ps
mA
mA
%
Third party brands and names are the property of their respective owners.
12
ICS92 48-98
Electrical Characteristics - REF, 48MHz, 24MHz
TA = 0 - 70C; V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
Output Low Voltage V
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter, Absolute
1
Guaranteed by design, not 100% tested in production.
= 3.3V +/-5%, V
DD
1
1
1
1
I
I
t
jabs5
OH5
OL5
OH5
OL5
t
r5
t
f5
d
= 2.5V +/-5%; CL = 20 pF (unless otherwise stated)
DDL
IOH = -12 mA 2.4 3.03 V
IOL = 10 mA 0.23 0.4 V
VOH = 2.0 V -50 -22
VOL = 0.8 V 16 40
VOL = 0.4 V, VOH = 2.4 V 1.26 4.0 ns
VOH = 2.4 V, VOL = 0.4 V 1.57 4.0 ns
t5
VT = 1.5 V 45 53.3 55 %
VT = 1.5 V
-1 0.25 1 ps
mA
mA
Third party brands and names are the property of their respective owners.
13
ICS92 48-98
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Third party brands and names are the property of their respective owners.
14
ICS92 48-98
SY MBOL
A 2.413 2.794 .095 .110
A 1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.63 5 BASIC 0.0 25 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
VA RIATIONS
N
28 9.398
34 11.303
48 15.748
56 18.288
64 20.828
In Millimeters
COMMON DIMENSIONS
MIN MAX MIN MAX
SEE VARIATIONS
SEE VARIATIONS
0° 8° 0° 8°
D mm.
MIN MAX MIN MAX
9.652
11.557
16.002
18.542
21.082
In Inc hes
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
D (inch)
.370 .38 0
.445 .45 5
.620 .63 0
.720 .73 0
.820 .83 0
J E D E C MO- 118
DO C # 10-0034
6/1/00
REV B
Ordering Information
ICS9248yF-98-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
15
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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