ICSI ICS9248-98 User Manual

Integrated Circuit

ICS9248-98

Systems, Inc.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Recommended Application:

440BX/VIA Apollo 133 style chipset.

Output Features:

• 2 - CPUs @2.5V, up to 166MHz.

• 1 - IOAPIC @ 2.5V

• 13 - SDRAM @ 3.3V

• 6 - PCI @3.3V,

• 1 - 48MHz, @3.3V fixed.

• 1 - 24MHz @ 3.3V

• 2 - REF @3.3V, 14.318MHz.

Features:

• Up to 166MHz frequency support

• Support power management: PCI, CPU stop and Mode

• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: <250ps

• PCI – PCI: <500ps

• BUFFER_IN-SDRAM: <5ns

• CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns

*PCI_STOP/REF0

VDD1

GND

VDD2

*MODE/PCICLK_F

**FS3/PCICLK0

GND PCICLK1 PCICLK2 PCICLK3 PCICLK4

VDD2

BUFFER IN

GND

SDRAM11 SDRAM10

VDD3 SDRAM9 SDRAM8

GND

SDATA

SCLK

* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND

Pin Configuration

1 2

X1 X2

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

ICS9248-98

48-Pin 300mil SSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

VDDL1 IOAPIC REF1/FS2* GND CPUCLK_F CPUCLK1 VDDL2 CLK_STOP#* SDRAM_F GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24MHz/FS1*

Block Diagram

PLL2

BUFFER IN

FS(3:0)

MODE

CLK_STOP#

PCI_STOP#

SDATA

SCLK

9248-98 Rev D 11/6/00

Third party brands and names are the property of their respective owners.

XTAL OSC

PLL1

Spread

Spectrum

LATCH

POR

Control

Logic

Config.

Reg.

PCI

CLOCK

DIVDER

STOP

48MHz 24MHz

IOAPIC

REF(1:0)

CPUCLK_F

CPUCLK 1

SDRAM (11:0) SDRAM_F

PCICLK (4:0) PCICLKF

Functionality

3SF2SF1SF0SF

0000 00.0800.04 0001 00.5705.73 0010 13.3856.14 0011 28.6614.33 0100 00.30133.43 0101 10.21143.73 0110 10.8610.43 0111 32.00114.33

1000 00.02100.04 1001 99.41133.83 1010 99.90166.63 1011 00.50100.53 1100 00.04100.53 1101 00.05105.73 1110 00.42100.13 1111 99.23152.33

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

UPC

KLCICP

)zHM(

ICS92 48-98

Pin Descriptions

REBMUNNIPEMANNIPEPYTNOITPIRCSED

11DDVRWPV3.3lanimon,ylppusrewopLATX,FER

,22,61,9,3

54,93,33

41XNI

52XTUO

41,62DDVRWPV3.3lanimon,KLCICPdnaF_KLCICProfylppuS

01,11,21,31)1:4(KLCICPTUO

51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI

,12,02,81,71

,23,13,92,82

83,73,53,43

63,03,913DDVRWP.V3.3lanimon,eroCLLPUPCdnaMARDSrofylppuS 32ATADSO/IIrofnipataD 42KLCSNIIfotupnikcolC

724DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP

04F_MARDSTUO#POTS_KLCybdetceffatoN.tuptuokcolcMARDSgninnureerF 14#POTS_KLCNI 242LDDVRWPlanimonV5.2skcolcUPCrofylppuS

341KLCUPCTUO

44F_KLCUPCTUO#POTS_KLCehtybdetceffatoN.kcolcUPCgninnureerF 64 74CIPAOITUOCIPAOI.1LDDVybderewoPzHM813.41.tuptuokcolc

841LDDVRWPlanimonV5.2,CIPAOIrofylppuS

0FERTUO.kcolcecnereferzhM813.41

#POTS_ICP

DNGRWPdnuorG

F_KLCICPTUO

2,1

EDOM

3SFNIDNGotnwod-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF

0KLCICPTUO

)0:11(MARDSTUO

zHM42TUOkcolctuptuozHM42

2,1

1SF

NI.tupnIdehctaL.niptcelesycneuqerF

zHM84TUOkcolctuptuozHM84

2,1

0SF

NItupnIdehctaL.niptcelesycneuqerF

1FERTUO.kcolcecnereferzHM813.41

2,1

2SF

NItupnIdehctaL.niptcelesycneuqerF

woltupninehw,level0cigoltaskcolcKLCICPstlaH

)0=EDOM,edomelibomnI(

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

)Fp63(pac

rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

.tnemeganam

.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf7niP

.tupnIdehctaL

wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP

)ylraeUPC(

wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP

)ylraeUPC(

nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS

.)tespihcybdellortnoc(

tnarelotV5yrtiucricC

tupnitnarelotV5,tupniC

skcolcMARDS&CIPAOI,KLCUPCstlahtupnisuonorhcnysasihT

.wolnevirdnehwlevel"0"cigolta

.2LDDVybderewop,stuptuokcolcUPC

woL=#POTS_KLCfiwoL

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

Third party brands and names are the property of their respective owners.

ICS92 48-98

General Description

The ICS9248-98 is a single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-98 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I stop clock programming and frequency selection.

C interface allows changing functions,

C programming.

Mode Pin - Power Management Input Control

7niP,EDOM

)tupnIdehctaL(

2niP

#POTS_ICP

)tupnI(

0FER

)tuptuO(

Power Groups

VDD1 = REF, X1, X2 VDD2 = PCICLK_F, PCICLK VDD3 = SDRAM, supply for PLL core VDD4 = 24MHz, 48MHz VDDL1 = IOAPIC VDDL2 = CPUCLK 1, CPUCLK_F

Third party brands and names are the property of their respective owners.

ICS92 48-98

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2  ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Write:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

(H)

ACK

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3  ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

ACK

Stop Bit

Byte Count

Byte

Byte 1

Byte

Byte 4

Byte

(H)

Notes:

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

Third party brands and names are the property of their respective owners.

C interface, the protocol is set to use only "Block-Writes" from the controller. The

Serial Configuration Command Bitmap

Byte0: Functionality and Frequency Select Register (default = 0)

tiBnoitpircseDDWP

)4,5,6,7,2(tiB

00000 00.0800.04 00001 00.5705.73 00010 13.3856.14 00011 28.6614.33 00100 00.30133.43 00101 10.21143.73 00110 10.8610.43 00111 32.00114.33 01000 00.02100.04 01001 99.41133.83 01010 99.90166.63 01011 00.50100.53 01100 00.04100.53 01101 00.05105.73 01110 00.42100.13

,2tiB 4:7tiB

01111 99.23152.33

10000 00.53157.33 10001 99.92105.23 100 10 00.62105.13 100 11 00.81133.93 10100 89.51166.83 10101 00.5976.13 10110 00.0900.03 10111 10.5843.82 11000 00.66105.14 11001 10.06100.04 11010 99.45157.83 11011 59.74199.63 11100 89.54105.63 11101 89.34199.53 11110 99.14105.53 11111 10.83105.43

3tiB 1tiB

0tiB

lamroN-0

gninnuR-0

stuptuollaetatsirT-1

KLCUPC

)zHM(

4:7,2tiBybdetcelessiycneuqerF-1

ICS92 48-98

KLCICP )zHM(

1010,0

1etoN

stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0

daerpSretneC%52.0±delbanEmurtcepSdaerpS-1

Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

Third party brands and names are the property of their respective owners.

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ICSI ICS9248-98 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual