ICSI ICS9248- 195 User Manual
Integrated
Circuit
Systems, Inc.
ICS9248-195
Frequency Generator & Integrated Buffers for PENTIUM II/III
Recommended Application:
440BX, MX, VIA PM/PL/PLE 133 style chip set, with
Coppermine or T ualatin processor , for note book
applications.
Output Features:
• 4 - CPUs @ 2.5V/3.3V
including 1 free running CPUCLK_F
• 9 - SDRAM @ 3.3V
• 7 - PCI @ 3.3V, including 1 free running PCICLK_F
• 1 - PCI Early @ 3.3V
• 1 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 137MHz frequency support
• 97MHz to support high-end AMD processor.
• Support power management: CLK, PCI, stop and
Po wer down Mode from I2C programming.
• Spread spectrum for EMI control
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter @ 2.5V: <300ps
• CPU Output Jitter @ 3.3V: <250ps
• PCI Output Jitter @ 3.3V: <250ps
• CPU Output Skew @ 2.5V : <175ps
• CPU Output Skew @ 3.3V : <175ps
• PCI Output Skew @ 3.3V : <500ps
• PCI Early to PCI Skew @ 3.3V: typ = 3ns
• SDRAM Output Skew @ 3.3V : <500ps
Pin Configuration
VDDREF
*SPREAD/REF0
GNDREF
*CPU2.5_3.3#/PCICLK_F
*SEL24_48#/PCICLK1
*SELPCIE_6#/PCICLK2
PCICLK6/
VDDPCI
*FS3/PCICLK0
GNDPCI
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
PCICLK_E
VDDCOR
PCI_STOP#
*Vtt_PWRGD/PD#
GND48
SDATA
SCLK
1
2
3
X1
X2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ICS9248-195
32
31
30
29
28
27
26
25
TM
& K6
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
Block Diagram
0375D—02/02/04
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Functionality
2tiB6tiB5tiB4tiBKLCUPCKLCICP
0000 76.6633.33
0001 00.00133.33
0010 76.6633.33
0011 33.33133.33
0100 76.6633.33
0101 00.00133.33
0110 00.00133.33
0111 33.33133.33
1000 76.6633.33
1001 00.00133.33
10 10 00.0900.03
10 11 33.33133.33
1100 00.0700.53
1101 00.50100.53
1110 33.33133.33
1111 00.04100.53
ICS9248-195
Pin Descriptions
NIP
REBMUN
1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR
2
0FERTUO sdaolSUBASIrofreffubREGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41
02#POTS_ICPNI )0=EDOM,edomelibomnI(woltupninehw,level0cigoltaskcolcKLCICPstlaH
,61,9,3
DNGRWPdnuorG
44,04,33
41XNI
52XTUO.zHM813.41yllanimon,tuptuolatsyrC
41,6ICPDDVRWPV3.3lanimonKLCICPdnaF_KLCICProfylppuS
7
2,1
8
3SF
01
11
21,31,71)3:5(KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.stuptuokcolcICP
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
81
E
91ROCDDVRWPV3.3.erocLLPehtrofniprewoP
12
1
#DP
2284DNGRWP.erocLLPdexif&sreffubtuptuozHM84&42ehtrofnipdnuorG
,23,13,92,82
83,73,53,43
63,03RDSDDVRWP.V3.3lanimon,eroCLLPUPCdnaMARDSrofylppuS
32ATADSNIIroftupniataD
42KLCSNIIfotupnikcolC
52
62
2,1
1SF
2,1
0SF
7284DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
93F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI .wolnevirdnehwlevel"0"cigoltaMARDS&,KLCUPCstlahtupnisuonorhcnysasihT
54,34,24)0:2(KLCUPCTUOUPCLDDVybderewop,stuptuokcolcUPC
64F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF
74UPCLDDVRWPV5.2skcolcUPCrofylppuS
84
1FERTUO.kcolcecnereferzHM813.41
2,1
2SF
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
EMANNIPEPYTNOITPIRCSED
2,1
DAERPS
NI "no"signidaerps,"hgiH"sitluafedpu-rewoP.tupnielbanemurtcepSdaerpShgiHevitcA
2Xmorfrotsiser
2,1
#3.3_5.2UPC
NI .tupnIdehctaL.UPCV3.3=WOL,UPCV5.2=hgiH.V3.3ro5.2siUPCLDDVrehtehwsetacidnI
F_KLCICPTUO .tnemeganamrewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
NI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP
2,1
#84_42LES
NIzHM84=woLnehwzHM84ro42rehtiestceleS
1KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP
2,1
#6_EICPLES
NI ).KLCICPylrae"hgiH"sitluafedpu-rewop81niprof(.tupnihctaltcelesICPlamronroylraEICP
2KLCICPTUO.tuptuokcolcKLCICP
-_KLCICP/6KLCICP
TUO #6_EICPLESybelbatcelestuptuokcolcICPylraerotuptuokcolcICP
DNGRWP_ttVNI
NI
)0:7(MARDSTUO .)tespihcybdellortnoc(nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
2
2
zHM84_42TUO01nipybelbatceleskcolctuptuozHM84rozHM42
NI.tupnIdehctaL.niptcelesycneuqerF
zHM84TUOkcolctuptuozHM84
NItupnIdehctaL.niptcelesycneuqerF
NItupnIdehctaL.niptcelesycneuqerF
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
.nipnwodrewopwolevitcasuonorhcnysa
.sm4nahtretaergebtonlliwnwodrewop
tupnitnarelotV5,tupnilairesC
tupnitnarelotV5,tupniC
nasinipehtretfaerehtnorewoptadehctaleblliwtcelesycneuqerfehthgihseog
DGRWP_ttVnehW.langis#DPdnaDGRWP_ttVrofniptupninoitcnuflaudasastcanipsihT
ehT.etatsrewopwolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
ehtfoycnetalehT.deppotseralatsyrcehtdnaOCVehtdnadelbasideraskcolclanretni
0375D—02/02/04
2
ICS9248-195
y
g
General Description
The ICS9248-195 is the single chip cloc k solution f or Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133
style chip set, with Coppermine or T ualatin processor , for Note book applications. It pro vides all necessary clock signals
for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-
195 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit PWD
0 = Center Spread Spec t rum M odul ation
Bit 7
1 = Down Spread S pec trum M odulation
FS3
FS2
FS1
FS0
Bit2
Bit6
Bit5
Bit4
0 0 0 0 66.67 33.33 ±0.35% -0.70%
0 0 0 1 100.00 33.33 ±0.35% -0.70%
0 0 1 0 66.67 33.33 ±0.60% -1.20%
0 0 1 1 133.33 33.33 ±0.35% -0.70%
0 1 0 0 66.67 33.33 ±0.23% -0.45%
Bit 2,
6:4
Bit 3
Bit 1
Bit 0
0 1 0 1 100.00 33.33 ±0.23% -0.45%
0 1 1 0 100.00 33.33 ±0.60% -1.20%
0 1 1 1 133.33 33.33 ±0.23% -0.45%
1 0 0 0 66.67 33.33 ±0.45% -0.90%
1 0 0 1 100.00 33.33 ±0.45% -0.90%
1 0 1 0 90.00 30.00 ±0.35% -0.70%
1 0 1 1 133.33 33.33 ±0.45% -0.90%
1 1 0 0 70.00 35.00 ±0.35% -0.70%
1 1 0 1 105.00 35.00 ±0.35% -0.70%
1 1 1 0 133.33 33.33 ±0.60% -1.20%
1 1 1 1 140.00 35.00 ±0.35% -0.70%
0 - Frequenc
1 - Frequency is c ontrolled by I
0 - Normal
1 - Spread Spec trum E nabl ed
0 - Runnin
1 - Tris t ate all out puts
is selected by hardware select pins. Lat ched input s.
Description
CPUCLK PCICLK
2
C programming.
Center
Spread %
Down
Spread%
Note1
0011
1
0
1
0
Notes:
1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011.
2, PWD = Power-Up Default
0375D—02/02/04
3
ICS9248-195
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB641 )siD/nE(F_KLCUPC
5tiB-0 )devreseR(
4tiB-0 )devreseR(
3tiB931 )siD/nE(F_MARDS
2tiB241 )siD/nE(2KLCUPC
1tiB341 )siD/nE(1KLCUPC
0tiB541 )siD/nE(0KLCUPC
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB71 )siD/nE(F_KLCICP
6tiB811 )siD/nE(6KLCICP
5tiB711 )siD/nE(5KLCICP
4tiB311 )siD/nE(4KLCICP
3tiB211 )siD/nE(3KLCICP
2tiB111 )siD/nE(2KLCICP
1tiB011 )siD/nE(1KLCICP
0tiB81 )siD/nE(0KLCICP
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-0 )devreseR(
5tiB-0 )devreseR(
4tiB-0 )devreseR(
3tiB821 )siD/nE(7MARDS
2tiB921 )siD/nE(6MARDS
1tiB131 )siD/nE(5MARDS
0tiB231 )siD/nE(4MARDS
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register v alues will be inv erted from pin values. Def ault latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
0375D—02/02/04
4
Byte 4: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-0 )devreseR(
5tiB-0 #)84_42LES(
4tiB-0 #0SFdehctaL
3tiB-0 #1SFdehctaL
2tiB-0 #2SFdehctaL
1tiB-0 #3SFdehctaL
0tiB-1 )devreseR(
Byte 5: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB431 )siD/nE(3MARDS
6tiB531 )siD/nE(2MARDS
5tiB731 )siD/nE(1MARDS
4tiB831 )siD/nE(0MARDS
3tiB621 )siD/nE(zHM84
2tiB521 )siD/nE(zHM42
1tiB841 )siD/nE(1FER
0tiB21 )siD/nE(0FER
ICS9248-195
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register v alues will be inverted from pin values. Default latch condition is for all latched inputs to be floating
(pulled up via internal resistor) at power-up.
0375D—02/02/04
5
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