ICSI ICS9148-11 User Manual

查询ICS9148-11供应商

Integrated
Circuit
Systems, Inc.

ICS9148-11

Frequency Generator & Integrated Buffers for PENTIUM

General Description Features

The ICS9148-11 generates all clocks required for high speed RISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.

High drive BCLK outputs typically provide greater than 1 V/ns slew
rate into 30 pF loads. PCLK outputs typically provide better than 1V/
ns slew rate into 20 pF loads while maintaining
The REF clock outputs typically provide better than 0.5V/ns slew
rates.

50±

5% duty cycle.

Block Diagram

 Generates four processor, six bus, one 14.31818MHz and 12

SDRAM clocks.

 Synchronous clocks skew matched to 250ps window on

CPU, SDRAM and 500ps window on BUS clocks.
 CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
 Test clock mode eases system design
 Custom configurations available
 VDD(1:3) - 3.3V ±10%

(inputs 5V tolerant w/series R )
 VDDL(1:2) - 2.5V or 3.3V ±5%
 PC serial configuration interface
 Power Management Control Input pins
 48-pin SSOP package

Pin Configuration

TM

9148-11 RevB 12/09/97P

48-Pin SSOP

Functionality

CPUCLK,

OE

SDRAM

(MHz)

0 High-Z High-Z High-Z
1 66.6 14.318 33.3

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

X1, REF

(MHz)

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

PCICLK

(MHz)

ICS9148-11

Pin Descriptions

PIN NUMBER PIN NAME TYPE DESCRIPTION

2 REF0 OUT 14.318 MHz reference clock output s.

3, 9, 16, 22, 27,

33, 39, 45

4X1 IN
5 X2 OUT

25 MODE IN Mode select pin for enabling power man agement features.

7 PCLK_F OU T Free running BUS clock dur ing PCI_STOP# = 0.

8, 10, 11, 12

13, 15

26 OE IN
23 SDATA IN Serial data in for serial config port.
24 SCLK IN Clock input f or serial config port.

1, 6, 14,

19, 30, 36,

17, 18, 20, 21,

32, 34, 35, 37, 38

42, 48 VDDL2, VDDL1 PWR

40, 41, 43, 44 CPUCLK (0:3) O UT CPU output cl ocks, powered by VDDL 2 (66.6 MHz)

46, 47 IO APIC (0 :1) OU T IOAPIC clock output , (14.318 MHz) powe red by VDDL1

28

29

31

GND PWR Ground.

XTAL_IN 14.318MHz Crystal input , has interna l 33pF load cap and f eed
back resistor from X2

XTAL_OUT Crystal output, has internal load cap 33pF

PCICLK (0:5) OUT BUS clock outputs.

Logic input for output enable, tristates all outputs when low.

VDD1, VDD2,
VDD3

SDRAM
(0:4) (8:11)

SDRAM7 OUT SDRAM clock 66.6 MHz selected
PCI_STOP# IN Halts PCICLK (0:5) at logic "0" level when low
SDRAM6 OUT SDRAM clock 66.6 MHz selected
CPU_STOP# IN Halts CPUCLK clocks at logic "0" level when low
SDRAM5 OUT SDRAM clock 66.6 MHz selected
PWR_DWN# IN Powers down chip, active low

PWR Nominal 3.3V power sup ply, see power groups for f unction.

OU T SDRAM clocks 66.6MHz.

CPU and IOAPIC cl ock power supply , either

2.5 or 3.3V nomi nal

Power Groups

VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,
SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)

2

Power-On Conditions

MODE P IN # DESCRIPTION FUNCTION

44, 43, 41, 40 CPUCLKs 66.6 MHz - w/serial config enable/disable

38, 37, 35, 34,

1

0

32, 31, 21, 20,

18, 17, 29, 28

8, 10, 11,

12, 14, 15, 7

28 PCI_STOP#

29 CPU_STOP#

31

7 PCICLK_F

44, 43, 41, 40 CPUCLKs

38, 37, 35,
34, 32, 21,

20, 18, 17

8, 10, 11,

12, 14, 15

SDRAM 66.6 MHz - All SDRAM outputs

PCICLKs 33.3 MHz - w/serial config enable/disable

Power Management, PCI (0:5) Clocks Stopped
when low

Power Management, CPU (0:3) Clocks Stopped
when low

SDRAM/PWR

_DWN#

SDRAM

PCICLKs

Used as PWR_DWN# when lo w

33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management

66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.

66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.

33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.

ICS9148-11

Example:
a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.
b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.

Power-On Default Conditions

At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.

CLOCK DEFAULT CONDITION AT POWER-UP

REF 0 14.31818 MHz

IOAPIC (0:1) 14.31818 MHz

3

ICS9148-11

Technical Pin Function Descriptions

VDD(1,2,3)

This is the power supply to the internal core logic of the device as well
as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B
and SDRAM(0:7).

This pin operates at 3.3V volts. Clocks from the listed buffers that it
supplies will have a voltage swing from Ground to this level. For the
actual guaranteed high and low voltage levels for the Clocks, please
consult the DC parameter table in this data sheet.

VDDL1,2

This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers that each supplies will have a voltage swing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.

GND

This is the power supply ground (common or negative) return pin for
the internal core logic and all the output buffers.

X1

This input pin serves one of two functions. When the device is used
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. This pin also implements an internal Crystal loading capacitor
that is connected to ground. With a nominal value fo 33pF no
external load cap is needed for a C

=17 to 18pF crystal.

L

X2

This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
output signal that drives (or excites) the discrete Crystal. The X2 pin
will also implement an internal Crystal loading capacitor nominally
33pF.

CPUCLK (0:3)

These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
Clocks are controlled by the Voltage level applied to the VDDL2 pin
of the device. See the Functionality Table for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.

SDRAM(0:11)

These Output Clocks are use to drive Dynamic RAMs and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAMs output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.

IOAPIC (0:1)

This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.

REF0

The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically

14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.

PCICLK (0:5)

These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification. They run at 1/2 CPU frequency.

MODE

This Input pin is used to select the Input function of the I/O pins. An
active Low will place the I/O pins in the Input mode and enable those
stop clock functions.

PWR_DWN#

This is an asynchronous active Low Input pin used to Power Down
the device into a Low Power state by not removing the power supply.
The internal Clocks are disabled and the VCO and Crystal are
stopped. Powered Down will also place all the Outputs in a low state
at the end of their current cycle. The latency of Power Down will not
be greater than 3ms. The I

2

C inputs will be Tri-Stated and the device
will retain all programming information. This input pin only valid when
MODE=0 (Power Management Mode)

CPU_STOP#

This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks including
SDRAM clocks will continue to run while this function is enabled.
The CPUCLKs will have a turn ON latency of at least 3 CPU
clocks. This input pin only valid when MODE=0 (Power Management
Mode)

PCI_STOP#

This is a synchronous active Low Input pin used to stop the PCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
Management Mode)

2

C

I

The SDATA and SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I
It will allow read-back of the registers. See configuration map for
register functions. The I

2

C specification in Philips I2C Peripherals

2

C protocol.

Data Handbook (1996) should be followed.

OE

Output Enable tristates the outputs when held low. This pin will
override the I
when the OE is low regardless of the I
is high, the I

2

C Byte 0 function, so that the outputs will be tristated

2

C function is in active control.

2

C defined function. When OE

4

General I2C serial interface information

A. For the clock generator to be addressed by an I

B. The clock generator is a slave/receiver I

C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

D. The input is operating at 3.3V logic levels.

E. The data byte format is 8 bit bytes.

F. To simplify the clock generator I

with an acknowledge bit between each byte.

Clock Generator

Address (7 bits)

A(6:0) & R/W#

D2

(H)

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.

Clock Generator

Address (7 bits)

A(6:0) & R/W#

(H)

D3

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.

ACK

ACK

+ 8 bits dummy

command code

2

C component. It can "read back "(in Philips I2C protocol) the data stored in the

Byte 0 ACK Byte 1 ACK

2

C interface, the protocol is set to use only block writes from the controller. The bytes

2

C controller, the following address must be sent as a start sequence,

ACK

+ 8 bits dummy

Byte count

ACK

Then Byte 0, 1, 2, etc in
sequence until STOP.

Byte 0, 1, 2, etc in sequence until STOP.

ICS9148-11

G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

maintain all prior programming information.

to a 1 (Enabled output state)

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (Default=0)

BIT PIN# DESCRIPTION PWD

Bit 7 - Reserved 0
Bit 6 - Must be 0 for normal operation 0

- Must be 0 for normal operation 0

Bit 5

Bit 4
Bit 3 - Reserved 0

Bit 2 - Reserved 0
Bit 1
Bit 0

In Spread Spectrum, Controls type
(0=centered, 1=down spread)

- Must be 0 for normal operation 0
In Spread Spectrum, Contro ls Spreading
(0=1.8%, 1=0.6%)

Bit1

1

-

1
0
0

Bit0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
0 - Normal operation

0

0

0
0

Note: PWD = Power-Up Default

5

ICS9148-11

Select Functions

FUNCTION

DESCRIPTION

CPU

PCI,

PCI_F

Tri - State Hi-ZHi-ZHi-ZHi-ZHi-Z

1

Test Mode TCLK/2

Notes:

1. REF is a test clock on the X1 inputs during test mode.

Byte 1: CPU Clock Register

BIT PIN# PWD DESCRIPTION

TCLK/4

Bit 7 - 1 Reserved
Bit 6 - 1 Reserved
Bit 5 - 1 Reserved
Bit 4 - 1 Reserved
Bit 3 40 1 CPUCLK3 (Act/Inact)
Bit 2 41 1 CPUCLK2 (Act/Inact)
Bit 1 43 1 CPUCLK1 (Act/Inact)
Bit 0 44 1 CPUCLK0 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

OUTPUTS

SDRAM REF IOAPIC

1

TCLK/2

1

Byte 2: PCICLK Clock Register

TCLK

1

BIT PIN# PWD DESCRIPTION

Bit 7 - 1 Reserve d
Bit 6 7 1 P CICLK_F (Act/Inact)
Bit 5 15 1 PCICLK5 (Act/Inact)
Bit 4 13 1 PCICLK4 (Act/Inact)
Bit 3 12 1 PCICLK3 (Act/Inact)
Bit 2 11 1 PCICLK2 (Act/Inact)
Bit 1 10 1 PCICLK1 (Act/Inact)
Bit 0 8 1 PCICLK0 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

TCLK

1

Byte 3: SDRAM Clock Register

BIT PIN# PWD DESCRIPTION

Bit 7 28 1

Bit 6 29 1

Bit 5 31 1

SDRAM7 (Act/Inact)
Desktop only

SDRAM6 (Act/Inact)
Desktop only

SDRAM5 (Act/Inact)

Desktop only
Bit 4 32 1 SDRAM4 (Ac t/Inact)
Bit 3 34 1 SDRAM3 (Ac t/Inact)
Bit 2 35 1 SDRAM2 (Ac t/Inact)
Bit 1 37 1 SDRAM1 (Ac t/Inact)
Bit 0 38 1 SDRAM0 (Ac t/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

Byte 4: SDRAM Clock Register

BIT PIN# PWD DESCRIPTION

Bit 7 - 1 Reserved
Bit 6 - 1 Reserved
Bit 5 - 1 Reserved
Bit 4 - 1 Reserved
Bit 3 17 1 SDRAM11 (Act/In act)
Bit 2 18 1 SDRAM10 (Act/Inact)
Bit 1 20 1 SDRAM9 (Act/Inact)
Bit 0 21 1 SDRAM8 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

6

ICS9148-11

Byte 5: Peripheral Clock Register

BIT PIN# PWD DESCRIPTION

Bit 7 - 1 Reserved
Bit 6 - 1 Reserved
Bit 5 46 1 IOAPIC1 (Act/Ina ct)
Bit 4 47 1 IOAPIC0 (Act/Ina ct)
Bit 3 - 1 Reserved
Bit 2 - 1 Reserved
Bit 1 - 1 Reserved
Bit 0 2 1 REF0(Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

Byte 6: Optional Register for Future

BIT PIN# PWD DESCRIPTION

Bit 7 - 1 Reserved
Bit 6 - 1 Reserved
Bit 5 - 1 Reserved
Bit 4 - 1 Reserved
Bit 3 - 1 Reserved
Bit 2

-1

Reserved
Bit 1 - 1 Reserved
Bit 0 - 1 Reserved

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.

Power Management

Clock Enable Configuration

Other Clocks,

CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK PCICLK

X X 0 Low Low S topped Off Off

0 0 1 Low Low Running Running Running
0 1 1 Low 33.3 MHz Runni ng Running Running
1 0 1 66.6 MHz Low Running Running Running
1 1 1 66.6 MHz 33.3 MHz Running Running Running

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock pulse coming out
of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a
large impact on the initial clock distortion also.

SDRAM,

REF,

IOAPICs

Crystal VCOs

ICS9148-11 Power Management Requirements

SIGNAL SIGNAL STATE

CPU_ STOP# 0 (Disabled)

1 (Enabled )

PCI_STOP# 0 (Disabled)

1 (Enabled )

PWR_DWN# 1 (Normal Operation)

0 (Power Down)

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.

2

1

2

1

4

No. of rising edges of free

3

Latency

running PCICLK

1
1
1
1

3mS

2max

7

ICS9148-11

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP #
is synchronized by the ICS9148-11. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks
will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9148-11.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9148-11. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-11 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse)
is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

(Drawing shown on next page.)

8

ICS9148-11

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous
active low input. This signal is synchronized internal by the ICS9148-11 prior to its control action of powering down the clock synthesizer.
Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state
and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3 mS. The power down
latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

9

ICS9148-11

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V

Ambient Operating Temperature . . . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = V

PARAMETER SYMBOL CONDITIONS MIN TY P MAX UNITS

Input Hi gh Voltage V

In put Low Vol t a ge V

Input Hi gh Current I

Input Low Current I
Input Low Current I

Operating I

IH

IL

IH
IL1
IL2

DD3.3OPCL

Supply Current

Ou t puts Disabled I

DD3.3OECL

Supply Current

Input Capac itance

Transi ti on Time

Settli ng Time

Clk Stabilization

Skew

1

1

1

1

1

C

IN

C

INX

T

trans

T

s

T

STAB

T

CPU-SDRAM2VT

T

CPU-PCI2VT

T

REF-IOAPICVT

= 3.3 V +/-5% (unless otherwise stated)

DDL

VIN = V

DD

VIN = 0 V; Inputs with no pull -up resistor s -5 2.0
VIN = 0 V; Inputs with pull-up re sistors -200 -100

= 0 pF; Select @ 66M 75 95 mA

= 0 pF ; With input addr e ss to Vdd or GND 1 8 25 mA

Logi c Inputs 5 pF
X1 & X2 pins 27 36 45 pF

To 1st crossing of target Freq. 3 ms
From 1st crossing to 1% target Fr e q. 5 ms
From VDD = 3.3 V to 1% target Freq. 5 3 ms

= 1.5 V 200 500 ps
= 1.5 V 1 2 4 ns

= 1.5 V

+0.5 V

DD

2V

+0.3 V

DD

VSS-0.3 0. 8 V

0.1 5

µ
µ
µ

900 ps

A
A
A

10

ICS9148-11

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating I

DD2.5OPCL

= 0 pF; Select @ 66M 6 8 9.5 m A

Supply Current

T

1

Skew

1

Guarenteed by design, not 10 0% teste d in producti o n.

CPU-SDRAM2VT

T

CPU-PCI2VT

T

REF-IOAPICVT

= 1.5 V; VTL = 1.25 V; SDRAM Leads 250 500 ps
= 1.5 V; VTL = 1.25 V; CPU Leads 1 2 4 ns

= 1.5 V; VTL = 1.25 V; CPU Leads

Electrical Characteristics - CPU

TA = 0 - 70C; VDD = 3.3 V +/-5%, V

PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
O ut put Impedance R
O ut put Impedance R

O utput High Voltag e V

Output Low Voltage V

Ou t put High Curre nt I

Output L ow Current I

Rise Time t

Fall Time t

Duty Cycle d

Skew t

Jitter t

1

Guarenteed by de sign, not 10 0% te sted in pr odu c t ion.

DSP2B

DSN2B

OH2BIOH

OL2B
OH2B
OL2B

r2B

f2B

t2B

sk2B

t

jcyc-cyc2B

j1s2B

t

jabs2B

= 2.5 V +/-5%; CL = 10 - 2 0 pF (unl ess otherwise stated)

DDL

1

VO = VDD*(0.5) 15 45

1

VO = VDD*(0.5) 15 45

= -12.0 mA 2 2.6 V
IOL = 12 mA 0.3 0.4 V
VOH = 1.7 V -25 -16 mA
VOL = 0.7 V 19 26 mA

1

VOL = 0.4 V, VOH = 2.0 V 1.7 2 ns

1

VOH = 2.0 V, VOL = 0.4 V 1.5 2 ns

1

VT = 1.25 V 45 50 55 %

1

VT = 1.25 V 60 250 ps

1

VT = 1.25 V 150 250 ps

1

VT = 1.25 V 30 150 ps

1

VT = 1.25 V

= 2.5 V +/-5% (unless otherwise stated)

DDL

860 ps

-250 80 +250 ps

Ω
Ω

11

ICS9148-11

Electrical Characteristics - IOAPIC

TA = 0 - 70C; VDD = 3.3 V +/-5%, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Impedance R
O ut put Impedance R

O utput High Voltag e V

Output Low Voltage V
Ou t put High Current I
Output L ow Current I

Rise Time t

Fall Time t

Duty Cycle d

Jitter t

1

Guarenteed by de sign, not 100% t e sted in producti o n.

DSP4B

DSN4B

OH4\BIOH

OL4B
OH4B
OL4B

r4B

f4B

t4B

t

jcyc-cyc4B

j1s4B

t

jabs4B

= 2.5 V +/-5%; CL = 10 - 2 0 pF (unl ess otherwise stated)

DDL

1

VO = VDD*(0.5) 10 30

1

VO = VDD*(0.5) 10 30

= -18 mA 2 2.4 V
IOL = 18 mA 0.45 0.5 V
VOH = 1.7 V -25 -16 mA
VOL = 0.7 V 19 26 mA

1

VOL = 0.4 V, VOH = 2.0 V 1.4 1.6 ns

1

VOH = 2.0 V, VOL = 0.4 V 1.2 1.6 ns

1

VT = 1.25 V 40 54 60 %

1

VT = 1.25 V 1400 ps

1

VT = 1.25 V 300 400 ps

1

VT = 1.25 V

Ω
Ω

-1000 800 1000 ps

Electrical Characteristics - REF0

TA = 0 - 70C; VDD = V

PARAMETER SYMBOL CONDITIONS MIN TY P MAX UNITS
O ut put Impedance R
O ut put Impedance R

O utput High Voltag e V

Output Low Voltage V

Ou t put High Curre nt I

Output L ow Current I

Rise Time T

Fall Time T

Duty Cycle D

Jitter t

1

Guarenteed by de sign, not 10 0% te sted in pr odu c t ion.

= 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)

DDL

DSP7

DSN7

OH7

OL7
OH7
OL7

r7

f7

t7

t

jcyc-cyc7B

j1s7B

t

jabs7B

VO = VDD*(0.5) 10 24
VO = VDD*(0.5) 10 24
IOH = -30 mA 2.6 2 .75 V
IOL = 23 mA 0.3 0.4 V
VOH = 2.0 V -62 -54 mA
VOL = 0.8 V 42 50 mA

1

VOL = 0.4 V, VOH = 2.4 V 0.9 2 ns

1

VOH = 2.4 V, VOL = 0.4 V 0.9 2 ns

1

VT = 1.5 V 40 54 60 %

1

VT = 1.25 V 1400 ps

1

VT = 1.25 V 350 ps

1

VT = 1.25 V

-1000 900 1000 ps

Ω
Ω

12

ICS9148-11

Electrical Characterist ics - PC I

TA = 0 - 70C; VDD = V

PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
O ut put Impedance R
O ut put Impedance R

O utput High Voltag e V

Output Low Voltage V

Ou t put High Curre nt I

Output L ow Current I

Rise Time t

Fall Time t

Duty Cycle d

Skew t

Jitter t

1

Guarenteed by de sign, not 100% t e sted in producti o n.

= 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)

DDL

1

DSP1

DSN1

OH1
OL1

sk1

j1s1

t

jabs1

OH1
OL1

r1

f1

t1

VO = VDD*(0.5) 12 55

1

VO = VDD*(0.5) 12 55
IOH = -11 mA 2.6 3.1 V
IOL = 9.4 mA 0.15 0.4 V
VOH = 2.0 V -65 -54 mA
VOL = 0.8 V 40 54 mA

1

VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns

1

VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns

1

VT = 1.5 V 45 50 55 %

1

VT = 1.5 V 200 500 ps

1

VT = 1.5 V 10 150 ps

1

VT = 1.5 V

-250 65 250 ps

Ω
Ω

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Impedance R
O ut put Impedance R

O utput High Voltag e V

Output Low Voltage V
Ou t put High Current I
Output L ow Current I

Rise Time T

Fall Time T

Duty Cycle D

Skew T

Jitter T

1

Guarenteed by de sign, not 100% t e sted in producti o n.

= 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)

DDL

1

VO = VDD*(0.5) 10 24

1

VO = VDD*(0.5) 10 24
IOH = -30 mA 2.6 2.8 V
IOL = 23 mA 0.3 0.4 V
VOH = 2.0 V -67 -54 mA
VOL = 0.8 V 40 55 mA

1

VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns

1

VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns

1

VT = 1.5 V 45 50 55 %

1

VT = 1.5 V 200 500 ps

1

VT = 1.5 V 50 150 ps

1

VT = 1.5 V

T

DSP3

DSN3

OH3

OL3
OH3
OL3

r3

f3

t3

sk3

j1s3

jabs3

-250 100 250 ps

Ω
Ω

13

ICS9148-11

SYMBOL COMMON DIMENSIONS VARIATIONS D N

MIN. NOM. MAX. MI N. NOM. MAX.

A .095 .101 .110 AC .620 .625 .630 48
A1 .008 .012 .016
A2 .088 .090 .092

B .008 .010 .0135

C.005- .010

D See Variations

E .292 .296 .299

e0.025 BSC

H .400 .406 .410

h .010 .013 .016
L .024 .032 .040
N See Variations

∝

X .085 .093 .100

0° 5° 8°

Ordering Information

ICS9148F-11

Example:

ICS XXXX F - PPP

SSOP Package

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest

14

version of all device data to verify that any information being relied upon by the
customer is current and accurate.