providing an output frequency range of 62.5MHz to 350MHz.
The output frequency can be programmed using the parallel interface, M0 through M8 to the configuration logic, and the output
divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-21 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes
which are controlled by the SSC_CTL[1:0] pins. Unlike other
synthesizers, the ICS8431-21 can immediately change
spread-spectrum operation without having to reset the device.
In SSC mode, the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes, the
PLL is disconnected as the source to the differential output
allowing an external source to be connected to the TEST_I/O
pin. This is useful for in-circuit testing and allows the differential output to be driven at a lower frequency throughout the
system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout
divide by 2. This is useful for characterizing the oscillator and
internal dividers.
The ICS8431-21 is a general purpose clock frequency synthesizer for IA64/32 application and a
member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
• Fully integrated PLL
• Differential 3.3V LVPECL output
• Crystal oscillator interface
• Output frequency range: 62.5MHz to 350MHz
• Crystal input frequency range: 14MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Programmable PLL loop divider for generating a variety
of output frequencies
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V supply voltage
• 0°C to 85°C ambient operating temperature
• Replaces ICS8431-01 and ICS8431-11
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAMPIN ASSIGNMENT
nP_LOAD
M0
V
M1
M2
M3
M4
M5
M6
M7
M8
V
1
2
3
4
5
6
7
8
9
10
11
12
EE
13
14
CC
XTAL_IN
XTAL_OUT
OSC
÷ 16
PHASE
DETECTOR
÷ M
PLL
VCO
÷2
÷4
FOUT
nFOUT
SSC_CTL0
SSC_CTL1
TEST_I/O
ICS8431-21
TEST_I/O
M0:M8
8431AM-21www.icst.com/products/hiperclocks.htmlREV. A APRIL 27, 2005
Configuration
Logic
nP_LOAD
SSC_CTL0
SSC
Control
Logic
SSC_CTL1
DIV_SEL
1
7.5mm x 18.05mm x 2.25mm package body
28-Lead SOIC
M Package
Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
XTAL_IN
XTAL_OUT
nc
nc
V
CCA
VEE
MR
DIV_SEL
V
CCO
FOUT
nFOUT
V
EE
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
The ICS8431-21 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the phase
detector.
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The PLL loop divider or M divider is programmed by using
inputs M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the
M0:M8 inputs will not be seen by the M divider until the next
LOW transition on nP_LOAD.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
the LVPECL output buffer. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8431-21 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fxtal
fVCO =
The M value and the required values of M0:M8 for programming
FOUT
Table 3B
fVCO
=
the VCO are shown in
Function Table. The frequency out is defined as follows:
For the ICS8431-21, the output divider may be set to either ÷2
or ÷4 by the DIV_SEL pin. For an input of 16 MHz, valid
M values for which the PLL will achieve lock are defined as:
250 ≤ M ≤ 511.
x
M
16
, Programmable VCO Frequency
fxtal x M
=
N
16 x N
8431AM-21www.icst.com/products/hiperclocks.htmlREV. A APRIL 27, 2005
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the
istics
is not implied. Exposure to absolute maximum rating
DC Characteristics
or
conditions for extended periods may affect product reliability.