ICSI ICS8427-02 User Manual
查询ICS8427DK-02供应商
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
ICS
HiPerClockS™
output frequency range of 15.625MHz to 500MHz. The
device powers up at a default output frequency of
200MHz with a 16.6667MHz crystal interface, and the
frequency can then be changed using the serial programming interface to change the M feedback divider and N
output divider. Frequency steps as small as 125kHz can
be achieved using a 16.6667MHz crystal and the output
divider set for ÷16. The low jitter and frequency range of the
ICS8427-02 make it an ideal clock generator for most
clock tree applications.
BLOCK DIAGRAM
The ICS8427-02 is a general purpose, six
LVHSTL output high frequency synthesizer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS8427-02 can support a very wide
ICS8427-02
500MHZ, LOW JITTER
FEATURES
• Six differential LVHSTL outputs
• Selectable crystal input interface or TEST_CLK input
• TEST_CLK accepts the following input types:
LVCMOS, LVTTL
• Output frequency range: 15.625MHz to 500MHz
• VCO range: 250MHz to 500MHz
• Serial interface for programming feedback and output dividers
• Supports SSC, -0.5% downspread. Can be enabled through
use of the serial programming interface.
• Output skew: 100ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• 2.5V core/1.8V output supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS-compliant
packages
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
MR
OE
S_LOAD
S_DATA
S_CLOCK
0
OSC
1
÷ 16
PHASE DETECTOR
÷ M
PLL
VCO
÷ 2
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
VCO_SEL
V
DD
nFOUT5
FOUT5
XTAL_IN
GND
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
nFOUT1
32 31 30 29 28 27 26 25
V
DDO
1
FOUT2
nFOUT2
÷ 1,
÷ 2,
÷ 4,
0
÷ 8,
÷ 16
1
FOUT0
nFOUT0
FOUT1
nFOUT1
FOUT2
nFOUT2
FOUT3
nFOUT3
FOUT4
nFOUT4
FOUT5
nFOUT5
FOUT3
nFOUT3
2
3
V
DDO
4
5
6
OE
7
8
GND
9 10 11 12 13 14 15 16
7mm x 7mm x 1.4mm package body
nFOUT0
V
DDO
FOUT0
FOUT1
ICS8427-02
V
nFOUT4
FOUT4
VDDTEST
32-Lead LQFP
DDO
Y Package
Top View
32-Lead VFQFN
TEST
5mm x 5mm x 0.75mm package body
K Package
Top View
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
1
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16.6667MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined in
the Input Frequency Characteristics, T ab le 6 NO TE 1.
The ICS8427-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16.6667MHz crystal, this
provides a 1.0417MHz reference frequency. The VCO of the
PLL operates over a range of 250MHz to 500MHz. The output of
the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS8427-02 powers up by default to 200MHz output frequency, using a 16.6667MHz crystal (M = 192, N = 2). The
output frequency can be changed after power-up by using the
serial interface to program the M feedback divider and the N
output divider.
ICS8427-02
500MHZ, LOW JITTER
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16.6667MHz
reference are defined as 120 ≤ M ≤ 240. The frequency out is
defined as follows:
Serial operation occurs when S_LOAD is LOW. The shift
register is loaded by sampling the S_DATA bits with the rising
edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output
divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input
is passed directly to the M divider and N outputdivider on each
rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output
as follows:
T1 T0 TEST Output
0 0 LOW
0 1 S_Data, Shift Register Input
1 0 Output of M divider
1 1 CMOS Fout
(Power-up
Default)
fout
=
fVCO
N
=
16
2Mfxtal
x
N
The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fxtal
fVCO =
S_CLOCK
S_DATA
S_LOAD
16
x 2M
T1 T0
tSt
H
N2
N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
Time
FIGURE 1. SERIAL LOAD OPERATIONS
NOTE: Default Output Frequency, using a 16.6667MHz crystal
on power-up = 200MHz (M = 192, N = 2) SSC off
t
S
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
2
Integrated
Circuit
Systems, Inc.
Test Mode
Control Register
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
M AND N DIVIDERS, SSC AND TEST MODE CONTROL BITS
N Divider
M Divider
ICS8427-02
500MHZ, LOW JITTER
SSC Control
Register
➤
➤
➤
S_DATA
➤
➤
1T0T2N1N0N8M7M6M5M4M3M2M1M0MCSS
➤
1T0T2N1N0N8M7M6M5M4M3M2M1M0MCSS
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
Shift Register
TEST Output
T1:T0 = 01
ICS8427-02 SHIFT REGISTER OPERATION – READ BACK CAPABILITY
1. Device powers up by default in Test Mode 01.
The Test Output in this case is wired to the shift register.
2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits.
Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched.
TEST Output
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
➤
➤
➤
➤
Data transfer from shift register
to M and N dividers and SSC and
Test Control Bits on a low-to-high
transition of S_LOAD.
S_CLOCK
S_DATA
S_LOAD
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
tSt
H
Time
Data transferred to M, N dividers, TEST and SSC Control Bits.
Changes to M, N, SSC and TEST mode bits take affect at this time.
Data latched into M, N Dividers, TEST and SSC control bits.
3
t
S
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
03,31,4,1V
3,2
6,5
7EOtupnIpulluP
61,8DNGrewoP.dnuorgylppusrewoP
9TSETtupt
62,01V
21,11
51,41
71RMtupnInwodlluP
81KCOLC_StupnIpulluP
91ATAD_StupnIpulluP
02DAOL_StupnInwodlluP
12V
22
32KLC_TSETtupnInwodlluP.slevelec
52,42
72LES_OCVtupnIpulluP
92,82
23,13
:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCn
ODD
,2TUOF
2TUOFn
,3TUOF
3TUOFn
DD
,4TUOF
4TUOFn
,5TUOF
5TUOFn
ADD
LES_LATX
,TUO_LATX
NI_LATX
,0TUOF
0TUOFn
,1TUOF
1TUOFn
rewoP.snipylppustuptuO
tuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
tu
ptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
uO
rewoP.snipylppuseroC
tuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
tuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
rewoP.nipylppusgolanA
tupnIpulluP
tupnI
tuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
tup
tuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
giHevitcA
retsaMhgiHevitcA
syrC
.tuptuoehtsiTUO_LATX
etniLTTVL/SOMCVL
iP,2elbaTeeS.srotsisertupnilanretniotrefer
ICS8427-02
500MHZ, LOW JITTER
.delbaneerastuptuoeht,HGIHnehW.elbanetuptuoh
.hgiH=xTUOFn,woL=xTUOF,WOLnehW
.slevelecafretniLTTVL/SOMCVL
.noitarepofoedomlairesehtniEVITCAsihcihwtuptuotseT
.slevelecafretniLTTVL/SOMCVL
sredividlanretnieht,HGIHcigolnehW.teseR
detrevniehtdnawologotxTUOFstuptuoeurtehtgnisuacteserera
hW.hgihogotxTUOFnstuptuo
.retsige
rtfihsehtotniATAD_SlairesdaolotkcolctupnI
.slevelecafretniLTTVL/SOMCVL
odelpmasataD.tupnilairesretsigertfihS
.slevelecafretniLTTVL/SOMCVL.KCOLC_S
htotniretsigertfihsmorfatadfonoitisnartslortnoC
.slevelecafretniLTTVL/SOMCVL
celeS.HGIHnehwtupniLATXstceleS.ecruos
.slevelecafretniLTTVL/SOMCVL.WOLnehw
afretniLTTVL/SOMCVL.tupnikcolctseT
.tupniehtsiNI_LATX.ecafretnirotallicsolat
.slevelecafr
sredividlanretnieht,WOLcigolne
.slevelecafretniLTTVL/SOMCVL.delbaneerastuptuoehtdna
foegdegnisirehtn
.sredivide
ecnereferLLPehtsatupnitsetrotupniLATXneewtebstceleS
KLC_TSETst
.edomssapybroLLPnisirezisehtnysrehtehwsenimreteD
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
R
PULLUP
R
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
NWODLLUP
ecnaticapaCtupnI 4Fp
rotsiseRpulluPtupnI 15kΩ
rotsiseRnwodlluPtupnI 15kΩ
4
Integrated
Circuit
Systems, Inc.
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
EOLES_LATXecruoSdetceleS5TUOF:0TUOF5TUOFn:0TUOFn
00 KLC_TSETWOL;delbasiDHGIH;delbasiD
01 TUO_LATX,NI_LA
10 KLC_TSETdelbanEdelbanE
11 TUO_LATX,NI_LATXdelbanEdelbanE
ninwohssa .2erugiF
TXWOL;delbasiDHGIH;delbasiD
ollofdelbanerodelbasiderastuptuokcolceht,sehctiwsEOretfA
ICS8427-02
500MHZ, LOW JITTER
egdeOCVgnillafdnagnisiragniw
nVCO
VCO
OE
nFOUT0:5
FOUT0:5
Disabled
FIGURE 2. OE TIMING DIAGRAM
Enabled
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
5
Integrated
Circuit
Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION T ABLE
ycneuqerFOCV
)zHM(
052021 00 1111000
80.252121 001111001
71.452221 00 11110 10
• • •••••••••
004291 0 11000000
• • •••••••••
29.794932 01110 1111
005042 011110000
ediviDM
6528214623618421
8M7M6M5M4M3M2M1M0M
NOTE 1
TABLE 3C. SERIAL MODE FUNCTION TABLE
stupnI
RMDAOL_SKCOLC_SATAD_S
HX X X .hgiH=xTUOFn,woL=xTUOF.WOLlaitnereffidstuptuosecroF.teseR
LL X X
LL
L
L
LL X X .sretsigertf
LH
↑
↓
↑ noitisnartegdegnisiR=
↓ noitisnartegdegnillaF=
↑
LataD .redividtuptuoNdnaredivi
LataD.dehctaleraseulavredividtuptuoNdnaredividM
↑
WOL=L:ETON
HGIH=H
eract'noD=X
ataD
ataD.dekcolcsitisaredividMotyltceriddessapATAD_S
snoitidnoC
.KCOLC_Sfoegde
qerftupninaotdnopserrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON
.sruccotnevelairesalitnuro
dMehtotdessaperaretsigertfihsehtfostnetnoC
ihstceffatonodtupnilaireS
.zHM7666.61foycneu
noitisna
rtWOLtxenlitnudedaolsniamerdnasretsigertupniotnidehctalsiataD
aenoATAD_SnoatadhtiwdedaolsiretsigertfihS.edomtupnilaireS
gnisirhc
TABLE 3D. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
tupnI
2N1N0NmuminiMmumixaM
000 2 521052
00 1 4 5.26521
010 8 52.135.26
011 61526.5152.13
10 0 1 052005
10 1 2 521052
110 4 5.26521
111 8 5
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
eulaVrediviDN
2.135.26
6
)zHM(ycneuqerFtuptuO
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Supply Voltage, V
Inputs, V
I
Outputs, I
Continuous Current 50mA
DD
O
4.6V
-0.5V to V
DD
Surge Current 100mA
Package Thermal Impedance, θ
JA
for 32 Lead LQFP 47.9°C/W (0 lfpm)
for 32 Lead VFQFN 34.8°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
V
ADD
V
ODD
I
DD
I
ADD
I
0DD
ylppuSeroC573.25.2526.2V
egatloVgolanA573.25.2526.2V
egatloVtuptuO6.18.10.2V
tnerruCylppuSrewoP 571Am
tnerruCylppuSgolanA 51Am
tnerruCylppuStuptuOdaoLoN0Am
+ 0.5V
= V
DD
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
= 2.5V±5%, V
DDA
= 1.8V±0.2V, TA = 0°C TO 70°C
DDO
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
V
HO
V
LO
tupnI
tupnI
tuptuO
tuptuO
egatloVhgiHtupnI 7.1V
egatloVwoLtupnI 3.0-7.0V
KLC_TSET,DAOL_S,RMV
tnerruChgiH
,LES_OCV,LES_LATX
EO,ATAD_S,KCOLC_S
KLC_TSET,DAOL_S,RM
tnerruCwoL
,LES_OCV,LES_LATX
EO,ATAD_S,KCOLC_S
egatloVhgiH
egatloVwoL
1ETON;TSET5.1V
1ETON;TSET 4.0V
05htiwdetanimretstuptuO:1ETON Ω Vot
.2/
ODD
DD
= V
DDA
V
= 2.5V±5%, V
V=
DD
NI
V=
DD
NI
=V526.2,
V
DD
V
V0=
NI
=,V526.2
V
DD
V0=
V
NI
= 1.8V±0.2V, TA = 0°C TO 70°C
DDO
3.0+V
DD
V526.2=051Aµ
V526.2=5Aµ
5-Aµ
051-Aµ
8427DY-02 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 17, 2006
7
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