2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug. The device operates up to 250MHz and is packaged
in a 16 TSSOP.
The ICS83058I is a low skew, 8:1, Single-ended
Multiplexer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS83058I has eight selectable singleended clock inputs and one single-ended clock
pin which may be set at 3.3V,
DDO
FEATURES
• 8:1 single-ended multiplexer
DD
DDO
= V
=3 .3V)
DDO
= 3.3V
DDO
= V
DD
= 3.3V
= 3.3V
DDO
• Q nominal output impedance: 7Ω (V
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), VDD = V
• Input skew: 225ps (maximum), V
• Part-to-part skew: 475ps (maximum), V
• Operating supply modes:
VDD/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAMPIN ASSIGNMENT
1
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
SEL2
SEL1
SEL0
OE
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
6
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
1.65V±5%
VDD,
V
DDO
LVCMOS
GND
-1.65V±5%
SCOPE
Qx
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
1.25V±5%
V
DD
V
LVCMOS
GND
DDO
Qx
SCOPE
1.25V±5%
VDD,
V
DDO
LVCMOS
GND
-1.25V±5%
SCOPE
Qx
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4±5%
V
0.9V±5%
DD
V
DDO
LVCMOS
GND
SCOPE
Qx
Part 1
Qx
Part 2
Qy
-0.9V±5%
V
DDO
2
V
DDO
2
tsk(pp)
-1.25V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V±5%
0.9V±5%
V
DD
V
LVCMOS
GND
-0.9V±5%
DDO
Qx
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUITPART-TO-PART SKEW
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
7
CLK0:CLK7
Q
Integrated
Circuit
Systems, Inc.
V
DD
2
V
DDO
2
tp
LH
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
V
DD
2
V
DDO
2
tp
HL
Clock
Outputs
20%
80%
t
R
80%
t
F
20%
CLKx
Q
CLKy
Q
INPUT SKEW
t
t
PD1
PD2
tsk(i) = ⏐t
PD2
– t
PD1
OUTPUT RISE/FALL TIMEPROPAGATION DELAY
V
DDO
t
PERIOD
t
PW
t
PERIOD
2
x 100%
Q
t
PW
odc =
⏐
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
8
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
RECOMMENDATIONSFOR UNUSED INPUT PINS
INPUTS:
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kW resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
9
Integrated
Circuit
Systems, Inc.
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
RELIABILITY INFORMATION
TABLE 6. θ
TRANSISTOR COUNT
The transistor count for ICS83058I is: 874
VS
. AIR FLOW TABLEFOR 16 LEAD TSSOP
JA
θθ
θ
θθ
Single-Layer PCB, JEDEC Standard Test Boards137.1°C/W118.2°C/W106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards89.0°C/W81.8°C/W78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
by Velocity (Linear Feet per Minute)
JA
0200500
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
10
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIXFOR 16 LEAD TSSOP
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
TABLE 7. PACKAGE DIMENSIONS
LOBMYS
N61
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.401.5
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
α
aaa--01.0
Reference Document: JEDEC Publication 95, MO-153
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83058AGIwww.icst.com/products/hiperclocks.htmlREV. A SEPTEMBER 27, 2005
12
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