ICSI ICS7151 User Manual

ICS7151

Spread Spectrum Clock Generator

Description

The ICS7151-10, -20, -40, and -50 are clock
generators for EMI (Electro Magnetic Interference)
reduction (see below for frequency ranges and
multiplier ratios). Spectral peaks can be attenuated by
slightly modulating the oscillation frequency. Both down
and center spread profiles are selectable. Down spread
maintains an average frequency less than an unspread
clock, and will not exceed the maximum frequency of
an unspread clock.

Block Diagram

2

S1:0

ENS

XIN

XOUT

Clock Buffer/

Crystal

Ocsillator

Features

• Operating voltage of 3.3 V ±0.3 V

• Packaged in 8-pin SOIC

• Available in Pb (lead) free package

• Input frequency range of 16.5 to 33.4 MHz

• Output frequency ranges of 8.3 to 16.7 MHz, 16.5 to

33.4 MHz, 33.3 to 66.7 MHz, 66.6 to 133.4 MHz

• Provides a spread spectrum clock output (±0.5%,

±1.5% center spread; -1.0%, -3.0% down spread)

• Multiplication rates of x1/2, x1, x2, and x4

• Advanced, low-power CMOS process

VDD

PLL Clock

Synthesis

and Spread

Spectrum

Circuitry

CKOUT

External caps required with crystal for
accurate tuning of the clock

GND

Product Lineup

Product Input Frequency Range Multiplier Ratio Output Frequency Range

ICS7151M-10, ICS7151MI-10 16.5 MHz to 33.4 MHz X1 16.5 MHz to 33.4 MHz

ICS7151M-20, ICS7151MI-20 16.5 MHz to 33.4 MHz X2 33.3 MHz to 66.7 MHz

ICS7151M-40, ICS7151MI-40 16.5 MHz to 33.4 MHz X4 66.6 MHz to 133.4 MHz

ICS7151M-50, ICS7151MI-50 16.5 MHz to 33.4 MHz X1/2 8.3 MHz to 16.7 MHz

MDS 7151 E 1 Revision 012306

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com

ICS7151

Spread Spectrum Clock Generator

Pin Assignment Spread Direction and Percentage

Select Table

XOUT

XIN 1

GND

S0

S1

2

3

4

8

VDD

7

ENS

6

5

CKOUT

S1

Pin 4

(note1)

0 0 Center ±1.5

0 1 Center ±0.5

S0

Pin 3

(note1)

Spread

Direction

Percentage (%)

Spread

8 pin (150 mil) SOIC

Pin Descriptions

Pin

Number

1 XIN Input Resonator connection pin/clock input pin.

2 GND Power Connect to ground.

3 S0 Input Select pin 0. Modulation rate setting pin.

4 S1 Input Select pin 1. Modulation rate setting pin.

5 CKOUT Output Modulated clock output pin.

6 ENS Input Modulation enable setting pin. Internal pull-up resistor.

7 VDD Power Connect to +3.3 V.

Pin

Name

10 Down -1.0

1 1 Down -3.0

ENS

(note 2)

0

1

Notes:

1. The modulation rate varies with input frequency.

2. Spread will default to ON when ENS pin is left open.

Pin Type Pin Description

Spread Spectrum

OFF

ON

8 XOUT Output Resonator connection pin.

MDS 7151 E 2 Revision 012306

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com

ICS7151

Spread Spectrum Clock Generator

External Components

The ICS7151 requires a minimum number of external
components for proper operation.

Decoupling Capacitor

A decoupling capacitor of 0.01µF must be connected
between GND and VDD on pin 7, as close to this pin as
possible. For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.

Series Termination Resistor

Series termination should be used on the clock output.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 27Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
25Ω.

PCB Layout Recommendations

For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.

underneath the device, or on layers adjacent to the
ground plane layer used by the device.

Crystal Information

The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:

Crystal caps (pF) = (C

In the equation, C
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.

is the crystal load capacitance. So,

L

- 6) x 2

L

Spread Spectrum Profile

The ICS7151 low EMI clock generator uses a triangular
frequency modulation profile for optimal down stream
tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.

1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.

2) To minimize EMI, the 27Ω series termination resistor
(if needed) should be placed close to the clock output.

3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS7151. This includes signal traces just

Modulation Rate

Frequency

Time

MDS 7151 E 3 Revision 012306

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com