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ICS650-27
Networking Clock Source
Description
The ICS650-27 is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 12.5 MHz or 25 MHz
clock or fundamental mode crystal input to produce
multiple output clocks for networking chips, PCI
devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V
designs.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other needed
clocks.
Features
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• Available in Pb (lead) free package
• 12.5 MHz or 25 MHz fundamental crystal or clock
input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Industrial temperature only
Block Diagram
25 or 12.5 MHz
cyrstal or clock
ACS1:0
BCS1:0
CCS
X1/ICLK
X2
VDD
2
CLKA1
2
2
Clock
Buffer/
Crystal
Oscillator
Clock
Synthesis
and Control
Circuitry
2
GND
/2
/2
OE (all outputs)
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT
MDS 650-27 D 1 Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
Pin Assignment
ICS650-27
Networking Clock Source
1ASC0
X2 BCS0
VDD CLKA1
ASC1
GND
CLKC1
CLKC2
CLKB2 DC
CLKB1
2
3X1/ICLK
4
5
7
8
9
10
20-pin (150 mil) SSOP
Pin Descriptions
Pin
Number
1 ACS0 Input A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3.
2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock
Pin
Name
20 BCS1
19
18 REFOUT
17
16
156
14
13
12
11
Pin
Typ e
VDD
OE
GND
CLKA2
CCS
Pin Description
input.
3 X1/ICLK Input Crystal connection. Connect to a fundamental crystal or clock input.
4 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 16.
5 ACS1 Input A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal
pull-up.
6 GND Power Connect to ground.
7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3.
8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1.
9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3.
10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3.
11 CCS Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3.
12 DC - Don’t connect. Do not connect anything to this pin.
13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3.
14 GND Power Connect to ground.
15 OE Input Output enable. Tri-states all outputs when low. Internal pull-up.
16 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 4.
17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3.
18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input.
19 BCS0 Input B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3.
20 BCS1 Input B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal
pull-up.
MDS 650-27 D 2 Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com