ICSI IC62VV12816LL-100T, IC62VV12816LL-70B, IC62VV12816LL-70BI, IC62VV12816LL-70T, IC62VV12816LL-70TI Datasheet
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IC62VV12816L
IC62VV12816LL
Document Title
128Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft April 23,2002 Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
LPSR024-0A 4/23/2002
IC62VV12816L
IC62VV12816LL
128K x 16 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access times: 70, 100 ns
• CMOS low power operation
I
CC1=7mA (typical)* operating
I
SB2=0.5µA (typical)* CMOS standby
* Typical values are measured at V
A=25°C
T
CC=1.8V,
• TTL compatible interface levels
• Single 1.65V-2.2V Vcc power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC62VV12816L and IC62VV12816LL are low-power,
2,097,152 bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using ICSI's high-performance CMOS
technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low
power consumption devices.
When CE is HIGH (deselected) or both LB and UB are HIGH,
the device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62VV12816L and IC62VV12816LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA.
A0-A16
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
128K x 16
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
LPSR024-0A 4/23/2002
IC62VV12816L
IC62VV12816LL
PIN CONFIGURATIONS
44-Pin TSOP-2
1
A4
2
A3
3
A2
4
A1
5
A0
6
CE
7
I/O0
8
I/O1
9
I/O2
10
I/O3
11
Vcc
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
12
13
14
15
16
17
18
19
20
21
22
GND
48-Pin TF-BGA (TOP View)
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
Vcc
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
A
B
C
D
E
F
G
H
1 2 3 4 5 6
A1
LB
I/O
I/O
GND
Vcc
I/O
I/O
NC
8
9
14
15
OE
UB A3
I/O10A5
I/O
11
I/O
12
I/O
13
NC
A8
A0
NC
NC
A14
A12
A9
A4
A6
A7
A16
A15
A13
A10
A2
CE I/O
I/O1I/O
I/O
3
I/O
4
I/O
5
WE
A11 NC
N/C
Vcc
GND
I/O
I/O
0
2
6
7
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (l/O0-I/O7)
UB Upper-byte Control (l/O8-I/O15)
N C No Connection
Vcc Power
GND Ground
TRUTH TABLE
I/O PIN
Mode
WEWE
WE
WEWE
Not Selected X H X X X High-Z High-Z Stand by
Output Disabled H L H X X High-Z High-Z Active
Read H L L L H DOUT High-Z Active
Write L L X L H DIN High-Z Active
CECE
CE
CECE
OEOE
OE
OEOE
LBLB
LB
LBLB
UBUB
UB I/O0/-I/O7 I/O8-I/O15 Power
UBUB
X L X H H High-Z High-Z Stand by
X L X H H High-Z High-Z Stand by
H L L H L High-Z DOUT
HLLLL DOUT DOUT
L L X H L High-Z DIN
LLXLL DIN DIN
Integrated Circuit Solution Inc. 3
LPSR024-0A 4/23/2002
IC62VV12816L
IC62VV12816LL
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 1.65V- 2.2V
Industrial –40°C to +85°C 1.65V - 2.2V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.4 V
TBIAS Temperature Under Bias –40 to + 85 °C
VCC Vcc related to GND –0.3 to + 2.4 V
TSTG Storage Temperature –65 to + 150 °C
PT Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –0.1 mA 1.4 — V
VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V
(1)
VIH
VIL
(2)
Input HIGH Voltage 1.4 VCC + 0.2 V
Input LOW Voltage –0.2 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED –1 1 µA
Notes:
1. VIH(max.) = VCC+2.0V for pulse width less than 10 ns.
IL(min.) = –2.0V for pulse width less than 10 ns.
2. V
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
4 Integrated Circuit Solution Inc.
LPSR024-0A 4/23/2002
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