Datasheet IC62VV12816LL-100T, IC62VV12816LL-70B, IC62VV12816LL-70BI, IC62VV12816LL-70T, IC62VV12816LL-70TI Datasheet (ICSI)

IC62VV12816L
IC62VV12816LL

Document Title

128Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM

Revision History

Revision No History Draft Date Remark

0A Initial Draft April 23,2002 Preliminary

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

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IC62VV12816L
IC62VV12816LL

128K x 16 1.8V ULTRA
LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access times: 70, 100 ns

• CMOS low power operation
I

CC1=7mA (typical)* operating

I

SB2=0.5µA (typical)* CMOS standby

* Typical values are measured at V

A=25°C

T

CC=1.8V,

• TTL compatible interface levels

• Single 1.65V-2.2V Vcc power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IC62VV12816L and IC62VV12816LL are low-power,
2,097,152 bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using ICSI's high-performance CMOS
technology. This highly reliable process coupled with innova­tive circuit design techniques, yields high-performance and low
power consumption devices.

When CE is HIGH (deselected) or both LB and UB are HIGH,
the device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IC62VV12816L and IC62VV12816LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA.

A0-A16

VCC
GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE
OE

WE

UB

LB

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

128K x 16

MEMORY ARRAY

COLUMN I/O

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IC62VV12816LL

PIN CONFIGURATIONS

44-Pin TSOP-2

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

7

I/O0

8

I/O1

9

I/O2

10

I/O3

11

Vcc

I/O4
I/O5
I/O6
I/O7

WE
A16
A15
A14
A13
A12

12
13
14
15
16
17
18
19
20
21
22

GND

48-Pin TF-BGA (TOP View)

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O15

37

I/O14

36

I/O13

35

I/O12

34

GND

33

Vcc

32

I/O11

31

I/O10

30

I/O9

29

I/O8

28

NC

27

A8

26

A9

25

A10

24

A11

23

NC

A
B
C
D

E
F

G
H

1 2 3 4 5 6

A1

LB

I/O

I/O

GND

Vcc

I/O

I/O

NC

8

9

14

15

OE

UB A3

I/O10A5

I/O

11

I/O

12

I/O

13

NC

A8

A0

NC

NC

A14

A12

A9

A4

A6

A7

A16

A15

A13

A10

A2

CE I/O

I/O1I/O

I/O

3

I/O

4

I/O

5

WE

A11 NC

N/C

Vcc

GND

I/O

I/O

0

2

6

7

PIN DESCRIPTIONS

A0-A16 Address Inputs
I/O0-I/O15 Data Input/Output

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

LB Lower-byte Control (l/O0-I/O7)
UB Upper-byte Control (l/O8-I/O15)

N C No Connection
Vcc Power
GND Ground

TRUTH TABLE

I/O PIN

Mode

WEWE

WE

WEWE

Not Selected X H X X X High-Z High-Z Stand by

Output Disabled H L H X X High-Z High-Z Active

Read H L L L H DOUT High-Z Active

Write L L X L H DIN High-Z Active

CECE

CE

CECE

OEOE

OE

OEOE

LBLB

LB

LBLB

UBUB

UB I/O0/-I/O7 I/O8-I/O15 Power

UBUB

X L X H H High-Z High-Z Stand by

X L X H H High-Z High-Z Stand by

H L L H L High-Z DOUT
HLLLL DOUT DOUT

L L X H L High-Z DIN
LLXLL DIN DIN

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IC62VV12816L
IC62VV12816LL

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 1.65V- 2.2V
Industrial –40°C to +85°C 1.65V - 2.2V

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.4 V
TBIAS Temperature Under Bias –40 to + 85 °C
VCC Vcc related to GND –0.3 to + 2.4 V
TSTG Storage Temperature –65 to + 150 °C
PT Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = –0.1 mA 1.4 — V

VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V

(1)

VIH
VIL

(2)

Input HIGH Voltage 1.4 VCC + 0.2 V

Input LOW Voltage –0.2 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED –1 1 µA

Notes:

1. VIH(max.) = VCC+2.0V for pulse width less than 10 ns.

IL(min.) = –2.0V for pulse width less than 10 ns.

2. V

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

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IC62VV12816L
IC62VV12816LL

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to 1.4V
Input Rise and Fall Times 5 ns
Input Reference Level 0.9V

Output Reference Level 0.9V
Output Load See Figures 1

AC TEST LOADS

OUTPUT

100 pF

Including

jig and

scope

1 TTL

OUTPUT

5 pF

Including

jig and

scope

1 TTL

Figure 1 Figure 2

IC62VV12816L POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-70 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

ICC1 Vcc Dynamic Operating VCC = 1.8V, Com. — 15 — 10 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 15 — 10

ICC2 Vcc Dynamic Operating VCC =1.8V, Com. — 2 — 2 mA

Supply Current IOUT = 0 mA, f = 1MHZ Ind. — 2 — 2

ISB2 CMOS Standby VCC = Max., Other inputs= 0 - VCC Com. — 35 — 35 µA

Current (CMOS Inputs) 1) CE ≥ VCC – 0.2V (CE controlled) Ind. — 50 — 50

2) LB/ UB ≥ VCC – 0.2V (LB/ UB controlled)

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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IC62VV12816L
IC62VV12816LL

IC62VV12816LL POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-70 -100

Symbol Parameter Test Conditions Typ

(2)

. Max . Typ

(2)

. Max. Unit

ICC1 Vcc Dynamic Operating VCC = 1.8V, CE ≤ VIL Com. 7 15 4 10 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. 7 15 4 10

ICC2 Vcc Dynamic Operating VCC = 1.8V, CE ≤ VIL Com. —2 —2 mA

Supply Current IOUT = 0 mA, f = 1MHZ Ind. — 2 — 2

ISB2 CMOS Standby VCC = Max., Other inputs= 0 - VCC Com. 0.5 5 0.5 5 µA

Current (CMOS Inputs) 1) CE ≥ VCC – 0.2V (CE controlled) Ind. — 10 — 10

2) LB/ UB ≥ VCC – 0.2V (LB/ UB controlled)

Note:

1. At f = f

2. Typical values are measured at Vcc=1.8V, Ta=25

READ CYCLE SWITCHING CHARACTERISTICS

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

°C, and are not guaranteed or tested.

(1)

(Over Operating Range)

-70 -100

Symbol Parameter Min. Max. Min. Max. Unit

tRC Read Cycle Time 70 — 100 — ns
tAA Address Access Time — 70 — 100 ns
tOHA Output Hold Time 10 — 15 — ns
tACE CE Access Time — 70 — 100 ns
tDOE OE Access Time — 35 — 50 ns

(2)

tHZOE
tLZOE
tHZCE
tLZCE

OE to High-Z Output — 25 — 30 ns

(2)

OE to Low-Z Output 5 — 5 — ns

(2)

CE to High-Z Output 0 25 0 30 ns

(2)

CE to Low-Z Output 10 — 10 — ns

tBA LB, UB Access Time — 70 — 100 ns
tHZB LB, UB o High-Z Output 0 25 0 35 ns
tLZB LB. UB to Low-Z Output 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output
loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

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IC62VV12816L
IC62VV12816LL

AC TEST LOADS

READ CYCLE NO.1

ADDRESS

D

OUT

AC WAVEFORMS
READ CYCLE NO. 2

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

PREVIOUS DATA VALID

(1,3)

(OE Controlled)

DATA VALID

t

OHA

t

RC

ADDRESS

t

AA

OE

t

DOE

t

CE

t

LZCE

LZOE

t

ACE

LB, UB

t

BA

t

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transitions.

HIGH-Z

LZB

IL.

DATA VALID

t

HZOE

t

HZCE

t

HZB

t

OHA

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IC62VV12816L
IC62VV12816LL

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-70 -100

Symbol Parameter Min. Max. Min. Max Unit

tWC Write Cycle Time 70 — 100 — ns
tSCE CE to Write End 65 — 80 — ns
tAW Address Setup Time to Write End 65 — 80 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWB LB, UB Valid to End of Write 60 — 80 — ns
tPWE WE Pulse Width 55 — 80 — ns
tSD Data Setup to Write End 30 — 40 — ns
tHD Data Hold from Write End 0 — 0 — ns

(3)

tHZWE
tLZWE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in
Figure 1.

2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

WE LOW to High-Z Output — 30 — 40 ns

(3)

WE HIGH to Low-Z Output 5 — 5 — ns

AC WAVEFORMS

CE

WE

UB, LB

D

OUT

D

(1,2)

(CE Controlled)

IN

t

SA

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCS

t

AW

t

PWE

t

PBW

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

HD

t

LZWE

t

HA

WRITE CYCLE NO. 1

ADDRESS

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE) [ (

LB) = (UB) ] (WE).

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IC62VV12816L
IC62VV12816LL

WRITE CYCLE NO. 2 (WE Controlled)

t

WC

ADDRESS

LOW

CE

WE

t

SA

UB, LB

D

OUT

D

IN

DATA UNDEFINED

WRITE CYCLE NO. 3 (UB / LB Controlled)

VALID ADDRESS

t

AW

t

PWE

t

PBW

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

t

HD

t

LZWE

HA

ADDRESS

CE

WE

UB, LB

OUT

D

D

LOW

DATA UNDEFINED

IN

t

HZWE

t

t

SD

WC

t

WORD 2

t

WC

ADDRESS 1 ADDRESS 2

t

SA

t

HA

t

SA

t

PBW

WORD 1

HIGH-Z

t

t

SD

DATAIN

VALID

HD

PBW

DATAIN

VALID

t

LZWE

t

t

HD

HA

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IC62VV12816L
IC62VV12816LL

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.0 2.2 V

IDR Data Retention Current Vcc = 1.2V, CE ≥ Vcc – 0.2V Com. (-L) — 15 µA

Com. (-LL) — 3

Ind. (-L) — 20

Ind. (-LL) — 5

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform 5 — ns

DATA RETENTION WAVEFORM (CE or LB/UB Controlled)

V

CC

1.65V

1.4V
V

DR

CE, LB/UB

GND

SDR

t

Data Retention Mode

CE ≥ V

CC

- 0.2V

t

RDR

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IC62VV12816L
IC62VV12816LL

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

70 IC62VV12816L-70T TSOP-2

IC62VV12816L-70B 6*8mm TF-BGA

100 IC62VV12816L-100T TSOP-2

IC62VV12816L-100B 6*8mm TF-BGA

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

70 IC62VV12816LL-70T TSOP-2

IC62VV12816LL-70B 6*8mm TF-BGA

100 IC62VV12816LL-100T TSOP-2

IC62VV12816LL-100B 6*8mm TF-BGA

Speed (ns) Order Part No. Package

70 IC62VV12816L-70TI TSOP-2

IC62VV12816L-70BI 6*8mm TF-BGA

100 IC62VV12816L-100TI TSOP-2

IC62VV12816L-100BI 6*8mm TF-BGA

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

70 IC62VV12816LL-70TI TSOP-2

IC62VV12816LL-70BI 6*8mm TF-BGA

100 IC62VV12816LL-100TI TSOP-2

IC62VV12816LL-100BI 6*8mm TF-BGA

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