ICSI IC62LV256-100JI, IC62LV256-100N, IC62LV256-100T, IC62LV256-100TI, IC62LV256-100U Datasheet
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IC62LV256
Document Title
32K x 8 Low Power SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0A Initial Draft October 5,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
ALSR007-0A 10/5/2001
IC62LV256
32K x 8 LOW VOLTAGE STATIC RAM
FEATURES
• Access time: 45, 70, 100 ns
• Low active power: 70 mW
• Low standby power
— 60 µW CMOS standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC62LV256 is a low power, 32, 768-word by 8-bit
static RAM. It is fabricated using ICSI's high-performance
CMOS double-metal technology.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
20 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IC62LV256 is pin compatible with other 32K x 8 SRAMs
in 300mil DIP and SOJ, 330mil SOP, and 8*13.4mm TSOP-1
packages.
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001
IC62LV256
PIN CONFIGURATION
28-Pin DIP, SOJ and SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTIONS
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TRUTH TABLE
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
CECE
OEOE
CE
OE I/O Operation Vcc Current
CECE
OEOE
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Integrated Circuit Solution Inc. 3
ALSR007-0A 10/5/2001
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