ICSI IC62LV12816DLL-55TI, IC62LV12816DLL-70B, IC62LV12816DLL-70BI, IC62LV12816DLL-70T, IC62LV12816DLL-70TI Datasheet
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Integrated Circuit Solution Inc. 1
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
Document Title
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft June 7,2002 Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
2 Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The ICSI IC62LV12816DL and IC62LV12816DLL are lowpower,2,097,152 bit static RAMs organized as 131,072 words
by 16 bits. They are fabricated using ICSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE1 is HIGH or when CE2 is low (deselected) or both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.
The IC62LV12816DL and IC62LV12816DLL are packaged in
the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TFBGA.
FUNCTIONAL BLOCK DIAGRAM
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access times: 55, 70, 100 ns
• CMOS low power operation
--60mW (typical)* operating
--3
µW (typical)* CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
• Fully static operation: no clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6x8mm TF-BGA
• CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at VCC=3.0V, TA=25°C
A0-A16
CE1, CE2
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
Preliminary
Integrated Circuit Solution Inc. 3
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
TRUTH TABLE
I/O PIN
Mode
WEWE
WEWE
WE
CE1CE1
CE1CE1
CE1
CE2CE2
CE2CE2
CE2
OEOE
OEOE
OE
LBLB
LBLB
LB
UBUB
UBUB
UB I/O0/-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X X High-Z High-Z Standby
X X L X X X High-Z High-Z Standby
X L H X H H High-Z High-Z Standby
Output Disabled H L H H L X High-Z High-Z Active
H L H H X L High-Z High-Z Active
Read H L H L L H DOUT High-Z Active
H L H L H L High-Z DOUT Active
HLHLL L DOUT DOUT Active
Write L L H X L H DIN High-Z Active
L L H X H L High-Z DIN Active
LLHXL L DIN DIN Active
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Input/Output
CE1 Chip Enable1 Input
CE2 Chip Enable2 Input, BGA only
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (l/O0-I/O7)
UB Upper-byte Control (l/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
48-Pin TF-BGA (TOP View)
PIN CONFIGURATIONS
44-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
CE2
I/O
8
UB A3
A4
CE1 I/O
0
I/O
9
I/O10A5
A6
I/O1I/O
2
GND
I/O
11
NC
A7
I/O
3
Vcc
Vcc
I/O12NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11 NC
4 Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –40 to +85 °C
VCC Vcc related to GND –0.3 to +4.0 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –1 mA 2.0 — V
VOL Output LOW Voltage IOL = 2.1 mA — 0.4 V
VIH
(1)
Input HIGH Voltage 2.2 VCC + 0.2 V
VIL
(2)
Input LOW Voltage
(1)
–0.2 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED –1 1 µA
Notes:
1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns.
2. V
IL(min.) = –2.0V for pulse width less than 10 ns.
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V- 3.6V
Industrial –40°C to +85°C 2.7V - 3.6V
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