ICSI IC62LV1008L-100B, IC62LV1008L-100BI, IC62LV1008L-55B, IC62LV1008L-55BI, IC62LV1008L-70B Datasheet
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IC62LV1008L
IC62LV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft January 3,2002 Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
1M x 8 LOW POWER and LOW VCC
CMOS STATIC RAM
FEATURES
• Access times of 55, 70, 100 ns
• CMOS Low power operation:
I
CC=15mA (typical)* operation
ISB2=2µA (typical)* standby
• Low data retention voltage: 1.5V (min.)
• Output Enable (OE) and Two Chip Enables
(CE1, CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh reguired
• Single 2.7V-3.6V power supply
• Wafer level burn in test mode
• Available in the know good die form and
48-pin 8*10mm TF-BGA
* Typical values are measured at VCC=3.0V, TA=25°C
DESCRIPTION
The ICSI IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using
ICSI's low voltage, six transistor (6T), CMOS technology. The
device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
When
CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable ( WE)
controls both writing and reading of the memory.
The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.
Preliminary
FUNCTIONAL BLOCK DIAGRAM
A0-A19
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
1024K x 8
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
PIN CONFIGURATIONS
48-Pin 8*10mm TF-BGA (TOP View)
1 2 3 4 5 6
A1
OE
A0
A
NC
A2
CE2
A5
A17
Vcc
A14
A12
A9
A4
A6
A7
A16
A15
A13
A10
CE1 NC
NC
I/O
I/O
NC
WE
A11 A19
NC A3
B
C
D
E
F
G
H
NC
I/O
GND
Vcc
I/O
NC
A18
NC
0
I/O
1
I/O
2
NC
3
NC
A8
PIN DESCRIPTIONS
A0-A19 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Data Input/Output
NC No Connection
I/O
4
Vcc
5
GND
6
I/O
7
NC
Vcc Power
GND Ground
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X X High-Z ISB1, ISB2
(POWER-DOWN) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
CE1CE1
CE1 CE2
CE1CE1
OEOE
OE I/O Operation Vcc Current
OEOE
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V - 3.6V
Industrial –40°C to +85°C 2.7V - 3.6V
Integrated Circuit Solution Inc. 3
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
VCC Vcc related to GND –0.3 to +4.0 V
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)(2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
o
A = 25
C, f = 1 MHz, VCC = 3.0 V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.0 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC –1 1 µA
Notes:
IH(max.) = VCC +2.0V for pulse width less than 10 ns.
1. V
1. VIL(min.) = –2.0V for pulse width less than 10 ns.
(1)
(2)
2.2 VCC + 0.3 V
–0.2 0.4 V
4 Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
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