ICSI IC62C1024AL-35WI, IC62C1024AL-45Q, IC62C1024AL-45QI, IC62C1024AL-45T, IC62C1024AL-45TI Datasheet
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IC62C1024AL
Document Title
128K x 8 Low Power CMOS SRAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft May 7,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
ALSR009-0A 5/7/2002
IC62C1024AL
128K x 8 LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35, 45, 55, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC62C1024AL is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ICSI's highperformance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62C1024L is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
A0-A16
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
512 x 2048
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
IC62C1024AL
PIN CONFIGURATION
32-Pin SOP and DIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN DESCRIPTIONS
A0-A16 Address Inputs
PIN CONFIGURATION
32-Pin 8x20mm TSOP-1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vcc Power
GND Ground
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to + 70°C 5V ± 10%
Industrial –40°C to + 85°C 5V ± 10%
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X X High-Z ISB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
CE1CE1
CE1 CE2
CE1CE1
OEOE
OE I/O Operation Vcc Current
OEOE
Integrated Circuit Solution Inc. 3
ALSR009-0A 5/7/2002
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