ICSI IC61SF25632D-9.5BI, IC61SF25632D-9.5TQ, IC61SF25632D-9.5TQI, IC61SF25632T-6.5TQ, IC61SF25632T-6.5TQI Datasheet
...
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 1
SSR020-0A 9/03/2002
Document Title
8Mb SyncBurst Flow through SRAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 3,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
2 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Flowthrough Mode operation.
• User-selectable Output Drive Strength with XQ Mode.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using
MODE input
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +3.3V, +10%, –5% core power supply
• Power-down snooze mode
• 2.5V or 3.3V I/O Supply
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
256K x 32, 256K x 36, 512K x 18
8Mb SYNCBURST Flow throughSRAMs
DESCRIPTION
ICSI's 8Mb SyncBurst Flowthrough SRAMs integrate a 512k x
18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
ApplicationsApplications
ApplicationsApplications
Applications
The ICSI SyncBurst Flowthrough SRAM family employs highspeed ,low-power CMOS designs that are fabricated using an
advanced CMOS process to provide Level 2 Cache applications supporting Pentium and PowerPC microprocessors
originally, the device now finds application ranging from DSP
main store to networking chip set support.
Controls
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.Bursts can be initiated
with either ADSP (Address Status Processor) or ADSC (Address
Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
FAST ACCESS TIME
Symbol -6.5 -7.5 -8.5 -9.5 Units
Flow tKQ 6.5 7.5 8.5 9.5 ns
Through tKC 7.5 8.5 10 11 ns
2-1-1-1 ICC1 270 260 240 230 mA
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 3
SSR020-0A 9/03/2002
BLOCK DIAGRAM
18/19
BINARY
COUNTER
GW
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17 18/19
ADDRESS
REGISTER
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
(T, D)CE
(T) CE
2
(T, D)
CE2
BWa
BWb
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
An-A0
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
BWa
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
4 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
SA
SACECE2
BWd
BWc
BWb
BWaSAVCC
GND
CLKGWBWEOEADSC
ADSP
ADV
SA
SA
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
A10
SASASASASA
SA
46 47 48 49 50
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE , CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
SA
CE2
SA
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
SA
NC
NC
SA
SA
SA
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
SA
NC
ADSP
ADSC
VCC
XQ
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
SA
NC
SA
SA
SA
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
GND/NC
SA
NC
SA
SA
SA
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
SA
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
Note:Ball R5 no connection is acceptable
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 5
SSR020-0A 9/03/2002
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
SA
SACECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
SA
SA
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
SASASASASASASA
SA
46 47 48 49 50
PIN CONFIGURATION
100-Pin TQFP (T Version)
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
6 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE , CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
SA
CE2
SA
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
SA
NC
NC
SA
SA
SA
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
SA
NC
ADSP
ADSC
VCC
XQ
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
SA
NC
SA
SA
SA
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
GND/NC
SA
NC
SA
SA
SA
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
SA
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
SA
SACECE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLKGWBWEOEADSC
ADSP
ADV
SA
SA
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
SASASASASASASA
46 47 48 49 50
256K x 36
Note:Ball R5 no connection is acceptable
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 7
SSR020-0A 9/03/2002
PIN CONFIGURATION
100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
SA
SACECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADV
SA
SA
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SASASASASASASA
46 47 48 49 50
256K x 36
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
8 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
PIN CONFIGURATION
119-pin PBGA (Top View)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE , CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQb Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
DQPa-DQPb Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
100-Pin TQFP (D Version)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
NC
VCCQ
NC
DQc4
VCCQ
Nc
DQd6
VCCQ
DQd8
NC
NC
NC
VCCQ
SA
CE2
SA
DQb2
NC
DQc4
DQc3
NC
VCC
DQd5
NC
DQd7
NC
DQPd
SA
SA
NC
SA
SA
SA
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
SA
NC
ADSP
ADSC
VCC
XQ
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
SA
SA
SA
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
GND/NC
SA
NC
SA
SA
SA
DQPa
NC
DQb7
NC
DQb5
VCC
NC
DQa3
NC
DQa2
NC
SA
SA
NC
VCCQ
NC
NC
NC
DQb8
VCCQ
DQb6
NC
VCCQ
DQa4
NC
VCCQ
NC
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
SA
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
SA
SACECE2
NCNCBWb
BWa
A18
VCC
GND
CLKGWBWEOEADSC
ADSP
ADV
SA
SA
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
GND/NC
VCC
XQ
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
SASASASASASASA
46 47 48 49 50
512K x18
Note:Ball R5 no connection is acceptable
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 9
SSR020-0A 9/03/2002
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa -BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE,CE2,CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQb Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
XQ Output Drive Control
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply : +3.3V
or 2.5V
ZZ Snooze Enable
DQPa-DQPb Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
512K x18
SA
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
SA
SACECE2
NCNCBWb
BWa
CE
2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADV
SA
SA
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
GND/NC
VCC
XQ
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
SASASA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SASASASASASASA
46 47 48 49 50
100-Pin TQFP (T Version)
Note:Pin 14 no connection is acceptable
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
10 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
Note:
There are pull-up devices on the MODE, XQ, SCD, and a pull down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above table.
TRUTH TABLE
Address
Operation Used
CECE
CECE
CE CE2
CE2CE2
CE2CE2
CE2
ADSPADSP
ADSPADSP
ADSP
ADSCADSC
ADSCADSC
ADSC
ADVADV
ADVADV
ADV
WRITEWRITE
WRITEWRITE
WRITE
OEOE
OEOE
OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L X X X X High-Z
Deselected, Power-down None L L X L X X X X High-Z
Deselected, Power-down None L X H H L X X X High-Z
Deselected, Power-down None L L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X X Q
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
PARTIAL TRUTH TABLE
Function
GWGW
GWGW
GW
BWEBWE
BWEBWE
BWE
BWaBWa
BWaBWa
BWa
BWBW
BWBW
BW
bb
bb
b
BWcBWc
BWcBWc
BWc
BWdBWd
BWdBWd
BWd
Read H H X X X X
Read H L H H H H
Write Byte 1 H L L H H H
Write All Bytes H L L L L L
Write All Bytes L X X X X X
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control MODE L Linear Burst
H or NC Interleaved Burst
Power Down Control ZZ L or NC Active
H Standby
Output Drive Control XQ L High Drive (Low Impedance)
H Low Drive (High Impedance)
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 11
SSR020-0A 9/03/2002
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.5 V
VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
12 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
V
OH Output HIGH Voltage IOH = –2.0 mA, VCCQ = 2.5V 1.7 — V
IOH = –4.0 mA, VCCQ = 3.3V 2.4 — V
VOL Output LOW Voltage IOL = 2.0 mA, VCCQ = 2.5V — 0.7 V
IOL = 8.0 mA, VCCQ = 3.3V — 0.4 V
V
IH Input HIGH Voltage VCCQ = 2.5V 1.7 VCCQ+ 0.3 V
VCCQ = 3.3V 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage VCCQ = 2.5V –0.3 0.7 V
VCCQ = 3.3V –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VCC (1) –2 2 µA
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH –2 2 µA
Notes:
1. The MODE, ZZ, XQ, pin14 pin has an internal pullup. and input leakage = ±10 µA .
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-6.5 -7.5 -8.5 -9.5
Parameter Test Conditions Symbol Max. Max. Max. Max. Unit
AC Operating Device Selected, ICC1 Com. 300 290 280 370 mA
Supply Current All Inputs ≤ VIL or ≥VIH Ind. 320 310 300 290 mA
OE = VIH, VCC = Max
f = 1/tKC
Clock Running Device Deselected, ICC2 Com. 110 100 90 90 mA
VCC = Max., Ind. 120 1 10 100 100 mA
All Inputs ≤ VIL or ≥VIH
f = 1/tKC
COMS Standby Device Deselected, ISB Com. 90 90 90 90 mA
VCC = Max., Ind. 100 1 00 100 100 mA
All Inputs ≤ 0.2V or
≥VCC -0.2V; f = 0
Power Down Mode VCC = Max Izz Com. 80 80 80 80 mA
ZZ ≥VCC - 0.2V Ind. 90 9 0 9 0 9 0 mA
f = 0,
All input ≤ 0.2V or ≥VCC - 0.2V
OPERATING RANGE
Range Ambient Temperature VCC VCCQ
Commercial 0°C to +70°C 3.3V, +10%, –5% 2.375–3.6V
Industrial –40°C to +85°C 3.3V, +10%, –5% 2.375–3.6V
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 13
SSR020-0A 9/03/2002
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V for 3.3V I/O
and Reference Level VCCQ/2V for 2.5V I/O
Output Load See Figures 1 and 2
CAPACITANCE (1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions:
TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST LOADS
Figure 1 Figure 2
Output
Buffer
Z
O
= 50Ω
1.5V for 3,3V I/O
V
CCQ
/2V for 2.5V I/O
50Ω
317Ω/1667Ω
5 pF
Including
jig and
scope
351
Ω
/1538Ω
OUTPUT
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
14 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6.5 -7.5 -8.5 -9.5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 1 0 — 11 — ns
tKQ Clock Access Time — 6.5 — 7.5 — 8.5 — 9.5 ns
tKQX
(1)
Clock High to Output Invalid 2.5 — 2.5 — 3.0 — 3.0 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
tKH Clock High Pulse Width 1.6 — 2 — 2.3 — 2.8 — ns
tKL Clock Low Pulse Width 1.6 — 2 — 2.3 — 2.8 — ns
tKQHZ
(1,2)
Clock High to Output High-Z — 3.1 — 3.1 — 3.5 — 4 ns
tOEQ
Output Enable to Output Valid
— 3.1 — 3.1 — 3.5 — 4 ns
tOELZ
(1,2)
Output Enable to Output Low-Z
0—0— 0 — 0—ns
tOEHZ
(1,2)
Output Enable to Output High-Z
— 3.0 — 3.0 — 3.5 — 4 ns
tAS Address Setup Time 1.5 — 1.5 — 1.5 — 1.5 — ns
tSS Address Status Setup Time 1.5 — 1.5 — 1.5 — 1.5 — ns
tWS Write Setup Time 1.5 — 1.5 — 1.5 — 1.5 — ns
tCES Chip Enable Setup Time 1.5 — 1.5 — 1.5 — 1.5 — ns
tAVS Address Advance Setup Time 1.5 — 1.5 — 1.5 — 1.5 — ns
tDS Data Setup time 1.5 — 1.5 — 1.5 — ns
tDH Data Hold time 0.5 — 0.5 — 0.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Setup Time 2 — 2 — 2 — 2 — cyc
tZZREC ZZ Recovery Time 2 — 2 — 2 — 2 — cyc
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 15
SSR020-0A 9/03/2002
READ/WRITE CYCLE TIMING: FLOW THROUGH
Single Read
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
Addresses
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQX
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
t
OEQ
t
OELZ
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
16 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
ZZ
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
ZZS
t
ZZREC
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 17
SSR020-0A 9/03/2002
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
-6.5 IC61SF25632T-6.5TQ 14*20*1.4mm LQFP
IC61SF25632D-6.5TQ 14*20*1.4mm LQFP
IC61SF25632D-6.5B 14*22mm PBGA
-7.5 IC61SF25632T-7.5TQ 14*20*1.4mm LQFP
IC61SF25632D-7.5TQ 14*20*1.4mm LQFP
IC61SF25632D-7.5B 14*22mm PBGA
-8.5 IC61SF25632T-8.5TQ 14*20*1.4mm TQFP
IC61SF25632D-8.5TQ 14*20*1.4mm TQFP
IC61SF25632D-8.5B 14*22mm PBGA
-9.5 IC61SF25632T-9.5TQ 14*20*1.4mm TQFP
IC61SF25632D-9.5TQ 14*20*1.4mm TQFP
IC61SF25632D-9.5B 14*22mm PBGA
Speed Order Part Number Package
-6.5 IC61SF25636T-6.5TQ 14*20*1.4mm LQFP
IC61SF25636D-6.5Q 14*20*1.4mm LQFP
IC61SF25636D-6.5B 14*22mm PBGA
-7.5 IC61SF25636T-7.5TQ 14*20*1.4mm LQFP
IC61SF25636D-7.5TQ 14*20*1.4mm LQFP
IC61SF25636D-7.5B 14*22mm PBGA
-8.5 IC61SF25636T-8.5TQ 14*20*1.4mm TQFP
IC61SF25636D-8.5TQ 14*20*1.4mm TQFP
IC61SF25636D-8.5B 14*22mm PBGA
-9.5 IC61SF25636T-9.5TQ 14*20*1.4mm TQFP
IC61SF25636D-9.5TQ 14*20*1.4mm TQFP
IC61SF25636D-9.5B 14*22mm PBGA
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
18 Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
Speed Order Part Number Package
-6.5 IC61SF51218T-6.5TQ 14*20*1.4mm LQFP
IC61SF51218D-6.5TQ 14*20*1.4mm LQFP
IC61SF51218D-6.5B 14*22mm PBGA
-7.5 IC61SF51218T-7.5TQ 14*20*1.4mm LQFP
IC61SF51218D-7.5TQ 14*20*1.4mm LQFP
IC61SF51218D-7.5B 14*22mm PBGA
-8.5 IC61SF51218T-8.5TQ 14*20*1.4mm TQFP
IC61SF51218D-8.5TQ 14*20*1.4mm TQFP
IC61SF51218D-8.5B 14*22mm PBGA
-9.5 IC61SF51218T-9.5TQ 14*20*1.4mm TQFP
IC61SF51218D-9.5TQ 14*20*1.4mm TQFP
IC61SF51218D-9.5B 14*22mm PBGA
Industrial Range: -40°C to 85°C
Speed Order Part Number Package
-6.5 IC61SF25632T-6.5TQI 14*20*1.4mm LQFP
IC61SF25632D-6.5TQI 14*20*1.4mm LQFP
IC61SF25632D-6.5BI 14*22mm PBGA
-7.5 IC61SF25632T-7.5TQI 14*20*1.4mm LQFP
IC61SF25632D-7.5TQI 14*20*1.4mm LQFP
IC61SF25632D-7.5BI 14*22mm PBGA
-8.5 IC61SF25632T-8.5TQI 14*20*1.4mm TQFP
IC61SF25632D-8.5TQI 14*20*1.4mm TQFP
IC61SF25632D-8.5BI 14*22mm PBGA
-9.5 IC61SF25632T-9.5TQI 14*20*1.4mm TQFP
IC61SF25632D-9.5TQI 14*20*1.4mm TQFP
IC61SF25632D-9.5BI 14*22mm PBGA
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Integrated Circuit Solution Inc. 19
SSR020-0A 9/03/2002
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Speed Order Part Number Package
-6.5 IC61SF25636T-6.5TQI 14*20*1.4mm LQFP
IC61SF25636D-6.5QI 14*20*1.4mm LQFP
IC61SF25636D-6.5BI 14*22mm PBGA
-7.5 IC61SF25636T-7.5TQI 14*20*1.4mm LQFP
IC61SF25636D-7.5TQI 14*20*1.4mm LQFP
IC61SF25636D-7.5BI 14*22mm PBGA
-8.5 IC61SF25636T-8.5TQI 14*20*1.4mm TQFP
IC61SF25636D-8.5TQI 14*20*1.4mm TQFP
IC61SF25636D-8.5BI 14*22mm PBGA
-9.5 IC61SF25636T-9.5TQI 14*20*1.4mm TQFP
IC61SF25636D-9.5TQI 14*20*1.4mm TQFP
IC61SF25636D-9.5BI 14*22mm PBGA
Speed Order Part Number Package
-6.5 IC61SF51218T-6.5TQI 14*20*1.4mm LQFP
IC61SF51218D-6.5TQI 14*20*1.4mm LQFP
IC61SF51218D-6.5BI 14*22mm PBGA
-7.5 IC61SF51218T-7.5TQI 14*20*1.4mm LQFP
IC61SF51218D-7.5TQI 14*20*1.4mm LQFP
IC61SF51218D-7.5BI 14*22mm PBGA
-8.5 IC61SF51218T-8.5TQI 14*20*1.4mm TQFP
IC61SF51218D-8.5TQI 14*20*1.4mm TQFP
IC61SF51218D-8.5BI 14*22mm PBGA
-9.5 IC61SF51218T-9.5TQI 14*20*1.4mm TQFP
IC61SF51218D-9.5TQI 14*20*1.4mm TQFP
IC61SF51218D-9.5BI 14*22mm PBGA
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