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IC61SF12836-10TQ
Datasheet (ICSI)
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Datasheet IC61SF12836-10B, IC61SF12836-10TQ, IC61SF12836-10TQI, IC61SF12836-12B, IC61SF12836-12TQ Datasheet (ICSI)

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IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 1
SSR018-0A 09/17/2001
Document Title
128K x 32 Flow Through SyncBurst SRAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 17,2001
IC61SF12832 IC61SF12836
2 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data inputs and control signals
• Pentium
TM
or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and 119-pin PBGA package
• Single +3.3V +10%, -5% power supply
• Power-down snooze mode
DESCRIPTION
The ICSI IC61SF12832 and IC61SF12836 are high-speed synchronous static RAM designed to provide a burstable, high­performance for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SF12832 and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
128K x 32, 128K x 36 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FAST ACCESS TIME
Symbol Parameter 7.5 8 8.5 10 12 Units
tKQ Clock Access Time 7.5 8 8.5 10 12 ns tKC Cycle Time 8.5 10 11 15 15 ns
Frenquency 117 100 90 66 66 MHz
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 3
SSR018-0A 09/17/2001
BLOCK DIAGRAM
17
BINARY
COUNTER
A16-A0
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0’
A0
A1
A1’
CLK
ADV
ADSC ADSP
15 17
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW4
CE
CE2
CE2
BW2
BW3
128K x 32, 128K x 36
MEMORY ARRAY
32
or
36
INPUT
REGISTERS
CLK
32
or
36
OE
4
32 or 36
OE
DQ[31:0] or DQ[35:0]
IC61SF12832 IC61SF12836
4 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus. A2-A16 Synchronous Address Inputs CLK Synchronous Clock ADSP Synchronous Processor Address
Status ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance BW1-BW4 Synchronous Byte Write Enable BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable
DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection VCC +3.3V Power Supply GND Ground VCCQ Isolated Output Buffer Supply:
+3.3V
ZZ Snooze Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 NC
A6A7CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
NC DQc1 DQc2
VCCQ
GND DQc3 DQc4 DQc5 DQc6
GND
VCCQ
DQc7 DQc8
GNDQ
VCC
NC
GND DQd1 DQd2
VCCQ
GND DQd3 DQd4 DQd5 DQd6
GND
VCCQ
DQd7 DQd8
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
100-Pin LQFP119-pin PBGA (Top View)
128K x 32
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 5
SSR018-0A 09/17/2001
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus. A2-A16 Synchronous Address Inputs CLK Synchronous Clock ADSP Synchronous Processor Address
Status ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance BW1-BW4 Synchronous Byte Write Enable BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable
DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection VCC +3.3V Power Supply GND Ground VCCQ Isolated Output Buffer Supply:
+3.3V ZZ Snooze Enable DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 DQPa
A6A7CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
DQPc
DQc1 DQc2
VCCQ
GND DQc3 DQc4 DQc5 DQc6
GND
VCCQ
DQc7 DQc8
GNDQ
VCC
NC
GND
DQd1 DQd2
VCCQ
GND
DQd3 DQd4 DQd5 DQd6
GND
VCCQ
DQd7 DQd8 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
100-Pin LQFP119-pin PBGA (Top View)
128K x 36
IC61SF12832 IC61SF12836
6 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
TRUTH TABLE
Address
Operation Used
CECE
CECE
CE CE2
CE2CE2
CE2CE2
CE2
ADSPADSP
ADSPADSP
ADSP
ADSCADSC
ADSCADSC
ADSC
ADVADV
ADVADV
ADV
WRITEWRITE
WRITEWRITE
WRITE
OEOE
OEOE
OE DQ
Deselected, Power-down None H X X X L X X X High-Z Deselected, Power-down None L X H L XXXXHigh-Z Deselected, Power-down None L L X L XXXXHigh-Z Deselected, Power-down None X X H H L X X X High-Z Deselected, Power-down None X L X H L X X X High-Z Read Cycle, Begin Burst External L H L L XXXXHigh-Z Read Cycle, Begin Burst External L H L H L X Read X High-Z Write Cycle, Begin Burst External L H L H L X Write X High-Z Read Cycle, Continue Burst Next X X X H H L Read L Q Read Cycle, Continue Burst Next X X X H H L Read H High-Z Read Cycle, Continue Burst Next H X X X H L Read L Q Read Cycle, Continue Burst Next H X X X H L Read H High-Z Write Cycle, Continue Burst Next X X X H H L Write X High-Z Write Cycle, Continue Burst Next H X X X H L Write X High-Z Read Cycle, Suspend Burst Current X X X H H H Read L Q Read Cycle, Suspend Burst Current X X X H H H Read H High-Z Read Cycle, Suspend Burst Current H X X X H H Read L Q Read Cycle, Suspend Burst Current H X X X H H Read H High-Z Write Cycle, Suspend Burst Current X X X H H H Write X High-Z Write Cycle, Suspend Burst Current H X X X H H Write X High-Z
PARTIAL TRUTH TABLE
Function
GWGW
GWGW
GW
BWEBWE
BWEBWE
BWE
BW1BW1
BW1BW1
BW1
BW2BW2
BW2BW2
BW2
BW3BW3
BW3BW3
BW3
BW4BW4
BW4BW4
BW4
Read H H X X X X Read H L H H H H Write Byte 1 H L L H H H Write All Bytes H LLLLL Write All Bytes L XXXXX
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 7
SSR018-0A 09/17/2001
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
1,0
0,1A1’, A0’ = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias -40 to +85
o
C
TSTG Storage Temperature -55 to +150
o
C PD Power Dissipation 1.6 W IOUT Output Current (per I/O) 100 mA VIN, VOUT Voltage Relative to GND for I/O Pins -0.5 to VCCQ + 0.3 V VIN Voltage Relative to GND for -0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND -0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static
voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
IC61SF12832 IC61SF12836
8 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0oC to +70oC 3.3V +10%, -5% Industrial -40oC to +85oC 3.3V +10%, -5%
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = -4.0 mA 2.4 − V VOL Output LOW Voltage IOL = 8.0 mA − 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL Input LOW Voltage -0.3 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VCCQ
(2)
Com. -2 2 µA
Ind. -5 5
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. -2 2 µA
Ind. -5 5
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
7.5 8 8.5 10 12
Symbol Parameter Test Conditions Ma x. Ma x. Ma x. M ax. M ax. Unit
ICC AC Operating Device Selected, Com. 270 250 230 190 170 mA
Supply Current All Inputs = VIL or VIH Ind.
−
260 240 200 180 OE = VIH, Vcc = Max. Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 50 50 50 50 50 mA
VCC = Max., Ind.
−
60 60 60 60 All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min.
IZZ Power-down ZZ = VCCQ Com. 10 10 10 10 10 mA
Mode Current Clock Running Ind.
−
15 15 15 15 All Inputs ≤ GND + 0.2V or ≥ Vcc - 0.2V
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc - 0.2V.
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 9
SSR018-0A 09/17/2001
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25
O
C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V
and Reference Level Output Load See Figures 1 and 2
AC TEST LOADS
Output Buffer
Z
O
= 50Ω
1.5V
50Ω
30 pF
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1
IC61SF12832 IC61SF12836
10 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
7.5 8 8.5 10 12
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fMAX Clock Frequency − 117 − 100 − 90 − 66 − 66 MHz tKC Cycle Time 8.5 − 10 − 11 − 15 − 15 − ns tKH Clock High Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tKL Clock Low Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tKQ Clock Access Time − 7.5 − 8 − 8.5 − 10 − 12 ns tKQX
(1)
Clock High to Output Invalid 2 − 2 − 2 − 2 − 2 − ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 − 0 − 0 − 0 − 0 − ns
tKQHZ
(1,2)
Clock High to Output High-Z 2 3.5 2 3.5 2 3.5 2 3.5 2 3.5 ns tOEQ Output Enable to Output Valid − 3.5 − 3.5 − 3.5 − 3.5 − 5ns tOELZ
(1,2)
Output Enable to Output Low-Z 0 − 0 − 0 − 0 − 0 − ns tOEHZ
(1,2)
Output Disable to Output High-Z − 3.5 − 3.5 − 3.5 − 3.5 − 3.5 ns tAS Address Setup Time 2 − 2 − 2 − 2 − 4 − ns tSS Address Status Setup Time 2 − 2 − 2 − 2 − 4 − ns tWS Write Setup Time 2 − 2 − 2 − 2 − 4 − ns tCES Chip Enable Setup Time 2 − 2 − 2 − 2 − 4 − ns tAVS Address Advance Setup Time 2 − 2 − 2 − 2 − 4 − ns tAH Address Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tSH Address Status Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tWH Write Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tCEH Chip Enable Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tAVH Address Advance Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 11
SSR018-0A 09/17/2001
READ/WRITE CYCLE TIMING
Single Read
Single Write
High-Z
High-Z
DATAOUT
DATAIN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQX
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
t
OEQ
t
OELZ
IC61SF12832 IC61SF12836
12 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
7.5 8 8.5 10 12
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8.5 − 10 − 11 − 15 − 15 − ns tKH Clock High Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tKL Clock Low Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tAS Address Setup Time 2 − 2 − 2 − 2 − 4 − ns tSS Address Status Setup Time 2 − 2 − 2 − 2 − 4 − ns tWS Write Setup Time 2 − 2 − 2 − 2 − 4 − ns tDS Data In Setup Time 2 − 2 − 2 − 2 − 4 − ns tCES Chip Enable Setup Time 2 − 2 − 2 − 2 − 4 − ns tAVS Address Advance Setup Time 2 − 2 − 2 − 2 − 4 − ns tAH Address Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tSH Address Status Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tDH Data In Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tWH Write Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tCEH Chip Enable Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tAVH Address Advance Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns
Note:
1. Tested with load in Figure 1.
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 13
SSR018-0A 09/17/2001
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IC61SF12832 IC61SF12836
14 Integrated Circuit Solution Inc.
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SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
7.5 8 8.5 10 12
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8.5 − 10 − 11 − 15 − 15 − ns tKH Clock High Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tKL Clock Low Time 3 − 4 − 4.5 − 4.5 − 4.5 − ns tKQ Clock Access Time − 7.5 − 8 − 8.5 − 10 − 12 ns tKQX
(1)
Clock High to Output Invalid 2 − 2 − 2 − 2 − 2 − ns tKQLZ
(1,2)
Clock High to Output Low-Z 0 − 0 − 0 − 0 − 0 − ns tKQHZ
(1,2)
Clock High to Output High-Z 2 3.5 2 3.5 2 3.5 2 3.5 2 3.5 ns tOEQ Output Enable to Output Valid − 3.5 − 3.5 − 3.5 − 3.5 − 5ns tOELZ
(1,2)
Output Enable to Output Low-Z 0 − 0 − 0 − 0 − 0 − ns tOEHZ
(1,2)
Output Disable to Output High-Z − 3.5 − 3.5 − 3.5 − 3.5 − 3.5 ns tAS Address Setup Time 2 − 2 − 2 − 2 − 4 − ns tSS Address Status Setup Time 2 − 2 − 2 − 2 − 4 − ns tCES Chip Enable Setup Time 2 − 2 − 2 − 2 − 4 − ns tAH Address Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tSH Address Status Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tCEH Chip Enable Hold Time 0.5 − 0.5 − 0.5 − 0.5 − 1.5 − ns tZZS ZZ Standby 2 − 2 − 2 − 2 − 2 − cyc tZZREC ZZ Recovery 2 − 2 − 2 − 2 − 2 − cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 15
SSR018-0A 09/17/2001
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
ZZ
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
ZZS
t
ZZREC
IC61SF12832 IC61SF12836
16 Integrated Circuit Solution Inc.
SSR018-0A 09/17/2001
ORDERING INFORMATION Commercial Range: 0
o
C to +70oC
Frequency Order Part Number Package
7.5 IC61SF12832-7.5TQ 14*20*1.4mm LQFP IC61SF12832-7.5B 14*22mm PBGA
8 IC61SF12832-8TQ 14*20*1.4mm LQFP
IC61SF12832-8B 14*22mm PBGA
8.5 IC61SF12832-8.5TQ 14*20*1.4mm LQFP IC61SF12832-8.5B 14*22mm PBGA
10 IC61SF12832-10TQ 14*20*1.4mm LQFP
IC61SF12832-10B 14*22mm PBGA
12 IC61SF12832-12TQ 14*20*1.4mm LQFP
IC61SF12832-12B 14*22mm PBGA
Industrial Range:
− −
− −
−40oC to +85oC
Frequency Order Part Number Package
8 IC61SF12832-8TQI 14*20*1.4mm LQFP
8.5 IC61SF12832-8.5TQI 14*20*1.4mm LQFP
10 IC61SF12832-10TQI 14*20*1.4mm LQFP 12 IC61SF12832-12TQI 14*20*1.4mm LQFP
IC61SF12832 IC61SF12836
Integrated Circuit Solution Inc. 17
SSR018-0A 09/17/2001
ORDERING INFORMATION Commercial Range: 0
o
C to +70oC
Frequency Order Part Number Package
7.5 IC61SF12836-7.5TQ 14*20*1.4mm LQFP IC61SF12836-7.5B 14*22mm PBGA
8 IC61SF12836-8TQ 14*20*1.4mm LQFP
IC61SF12836-8B 14*22mm PBGA
8.5 IC61SF12836-8.5TQ 14*20*1.4mm LQFP IC61SF12836-8.5B 14*22mm PBGA
10 IC61SF12836-10TQ 14*20*1.4mm LQFP
IC61SF12836-10B 14*22mm PBGA
12 IC61SF12836-12TQ 14*20*1.4mm LQFP
IC61SF12836-12B 14*22mm PBGA
Industrial Range:
− −
− −
−40oC to +85oC
Frequency Order Part Number Package
8 IC61SF12836-8TQI 14*20*1.4mm LQFP
8.5 IC61SF12836-8.5TQI 14*20*1.4mm LQFP
10 IC61SF12836-10TQI 14*20*1.4mm LQFP 12 IC61SF12836-12TQI 14*20*1.4mm LQFP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
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