ICSI IC61LV6416-10B, IC61LV6416-10BI, IC61LV6416-8T, IC61LV6416-8TI, IC61LV6416-10K Datasheet
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IC61LV6416
Document Title
64K x 16 Hight Speed SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 12,2001
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
AHSR026-0A 09/12/2001
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IC61LV6416
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10, 12, and 15 ns
• CMOS low power operation
— 250 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC61LV6416 is a high-speed, 1,048,576-bit static
RAM organized as 65,536 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC61LV6416 is packaged in the JEDEC standard 44-pin
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TFBGA.
A0-A15
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
64K x 16
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
AHSR026-0A 09/12/2001
IC61LV6416
PIN CONFIGURATIONS
44-Pin SOJ
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
NC
A9
A8
A7
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2
3
4
5
6
7
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13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin TSOP-2
CE
A9
A8
A7
NC
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2
3
4
5
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7
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9
10
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12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
A12
A11
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
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2
3
4
5
48-Pin 6x8mm TF-BGA
1 2 3 4 5 6
A7
OE
UB A2
I/O2A0
I/O
3
I/O
4
I/O
6
NC
A12
A3
NC
NC
A9
A11
A13
A1
A4
A5
NC
A8
A10
A14
A
B
C
D
E
F
G
H
LB
I/O
I/O
GND
Vcc
I/O
I/O
NC
0
1
5
7
A6
CE I/O
I/O13I/O
I/O
12
I/O
11
I/O
10
WE
A15 NC
N/C
Vcc
GND
I/O
I/O
15
14
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8
PIN DESCRIPTIONS
A0-A15 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
TRUTH TABLE
I/O PIN
Mode
WEWE
WE
WEWE
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
CECE
CE
CECE
OEOE
OE
OEOE
LBLB
LB
LBLB
UBUB
UB I/O0-I/O7 I/O8-I/O15 Vcc Current
UBUB
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Integrated Circuit Solution Inc. 3
AHSR026-0A 09/12/2001
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