ICSI IC61LV5128-10K, IC61LV5128-10KI, IC61LV5128-10T, IC61LV5128-10TI, IC61LV5128-12K Datasheet

IC61LV5128

Document Title

512K x 8 Hight Speed SRAM with 3.3V

Revision History

Revision No History Draft Date Remark

0A Initial Draft September 11,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution, Inc. 1

AHSR021-0A 09/11/2001

IC61LV5128

512K x 8 HIGH-SPEED CMOS STATIC RAM

FEATURES

• High-speed access times:
— 8, 10, 12 and 15 ns

• High-preformance, lower-power CMOS process

• Multiple center power and ground pins for
greater noise immunity

• Easy memory expansion with CE and OE
options

• CE power-down

• Fully static operation: no clock or refresh
reguired

• TTL compatible inputs and outputs

• Single 3.3V ± 10% power supply

• Packages available:
— 36-pin 400mil SOJ
— 44-pin TSOP-2

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IC61LV5128 is a very high-speed, low power,
524,288-word by 8-bit COMS static RAM. The IC61LV5128 is
fabricated using ICSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher preformance and low power
consumotion devices.

When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.

The IC61LV5128 operates from a single 3.3V power supply and
all inputs are TTL-compatible.

The IC61LV5128 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.

A0-A18

VCC

GND

I/O0-I/O7

CE
OE
WE

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

512K X 8

MEMORY ARRAY

COLUMN I/O

2 Integrated Circuit Solution, Inc.

AHSR021-0A 09/11/2001

IC61LV5128

PIN CONFIGURATION

36-Pin SOJ

A0
A1
A2
A3
A4

CE
I/O0
I/O1

Vcc

GND

I/O2
I/O3

WE

A5
A6
A7
A8
A9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

PIN DESCRIPTIONS

NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC

PIN CONFIGURATION

44-Pin TSOP-2

TRUTH TABLE

NC
NC

CE
I/O0
I/O1

Vcc

GND

I/O2
I/O3

WE

NC

NC

44

1
2
3

A0

4

A1

5

A2

6

A3

7

A4

8
9
10
11
12
13
14
15
16

A5

17

A6

18

A7

19

A8

20

A9

21
22

NC

43

NC

42

NC

41

A18

40

A17

39

A16

38

A15

37

OE

36

I/O7

35

I/O6

34

GND

33

Vcc

32

I/O5

31

I/O4

30

A14

29

A13

28

A12

27

A11

26

A10

25

NC

24

NC

23

NC

A0-A18 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Input/Output

Mode

WEWE

WE

WEWE

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC

CECE

OEOE

CE

OE I/O Operation Vcc Current

CECE

OEOE

Vcc Power
GND Ground
NC No Connection

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Integrated Circuit Solution, Inc. 3

AHSR021-0A 09/11/2001