ICSI IC61LV25616-10KI, IC61LV25616-10T, IC61LV25616-12B, IC61LV25616-12BI, IC61LV25616-12K Datasheet
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IC61LV25616
Integrated Circuit Solution Inc. 1
AHSR022-0A 09/11/2001
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Document Title
256K x 16 Hight Speed SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 11,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC61LV25616
2 Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
FEATURES
• High-speed access time: 8, 10, 12, and 15 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
DESCRIPTION
The ICSI IC61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC61LV25616 is packaged in the JEDEC standard
44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TFBGA.
FUNCTIONAL BLOCK DIAGRAM
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
IC61LV25616
Integrated Circuit Solution Inc. 3
AHSR022-0A 09/11/2001
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PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
TRUTH TABLE
I/O PIN
Mode
WEWE
WEWE
WE
CECE
CECE
CE
OEOE
OEOE
OE
LBLB
LBLB
LB
UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
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20
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22
44
43
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A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
PIN CONFIGURATIONS
44-Pin TSOP-2 and SOJ
48-Pin TF-BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
N/C
I/O
0
UB A3
A4
CE I/O
8
I/O
1
I/O2A5
A6
I/O10I/O
9
GND
I/O
3
A17
A7
I/O
11
Vcc
Vcc
I/O4NC
A16
I/O
12
GND
I/O
6
I/O
5
A14
A15
I/O
13
I/O
14
I/O
7
NC
A12
A13
WE
I/O
15
NC
A8
A9
A10
A11 NC
IC61LV25616
4 Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage
(1)
–0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VCC Com. –1 1 µA
Outputs Disabled Ind. –5 5
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 350 — 320 — 290 — 260 m A
Supply Current IOUT = 0 mA, f = fMAX Ind. — 360 — 330 — 300 — 270
ISB1 TTL Standby Current VCC = Max., C om. — 55 — 55 — 55 — 55 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 65 — 65 — 65 — 65
CE ≥ VIH , f = 0
ISB2 CMOS Standby VCC = Max., Com . — 10 — 10 — 10 — 10 mA
Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias –45 to +90 °C
VCC Vcc Related to GND –0.3 to +4.0 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these
or any other conditions above those
indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
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