ICSI IC61LV256-10J, IC61LV256-10JI, IC61LV256-10T, IC61LV256-10TI, IC61LV256-12J Datasheet
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IC61LV256
Document Title
32K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0A Initial Draft April 19,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
AHSR027-0A 04/19/2002
IC61LV256
32K x 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
• High-speed access times:
-- 8, 10, 12, 15 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
600 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IC61LV256 is available in the JEDEC standard 28-pin,
300mil SOJ and the 8*13.4mm TSOP-1 package.
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
IC61LV256
PIN CONFIGURATION
28-Pin SOJ
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
I/O0
I/O1
I/O2
GND
PIN DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
TRUTH TABLE
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
CECE
OEOE
CE
OE I/O Operation Vcc Current
CECE
OEOE
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias Com. –10 to +85 °C
Ind. –45 to +90
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc. 3
AHSR027-0A 04/19/2002
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