ICSI IC61C632A-4PQ, IC61C632A-4PQI, IC61C632A-4TQ, IC61C632A-4TQI, IC61C632A-5PQ, IC61C632A-5TQ, IC61C632A-6PQ, IC61C632A-6PQI, IC61C632A-6TQ, IC61C632A-6TQI, IC61C632A-7PQ, IC61C632A-7PQI, IC61C632A-7TQ, IC61C632A-7TQI, IC61C632A-8PQ, IC61C632A-8PQI, IC61C632A-8TQ, IC61C632A-8TQI Datasheet

Loading...

IC61C632A

Document Title

32K x 32 Pipelined Sync. SRAM

Revision History

Revision No

History

Draft Date

Remark

0A

Initial Draft

September 13,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc.

1

SSR015-0A 09/13/2001

IC61C632A

32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

FEATURES

• Fast access time:

– 4 ns-125 MHZ; 5 ns-100 MHz;

6ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz

Internal self-timed write cycle

Individual Byte Write Control and Global Write

Clock controlled, registered address, data and control

Pentium™ or linear burst sequence control using MODE input

Three chip enables for simple depth expansion and address pipelining

Common data inputs and data outputs

Power-down control by ZZ input

JEDEC 100-Pin LQFP and PQFP package

Single +3.3V power supply

Two Clock enables and one Clock disable to eliminate multiple bank bus contention.

Control pins mode upon power-up:

MODE in interleave burst mode

ZZ in normal operation mode

These control pins can be connected to GNDQ or VCCQ to alter their power-up state

DESCRIPTION

The ICSI IC61C632A is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 32,768 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61C632A and controlled by the ADV (burst address advance) input pin.

Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst.

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

2

Integrated Circuit Solution Inc.

 

SSR015-0A 09/13/2001

ICSI IC61C632A-4PQ, IC61C632A-4PQI, IC61C632A-4TQ, IC61C632A-4TQI, IC61C632A-5PQ, IC61C632A-5TQ, IC61C632A-6PQ, IC61C632A-6PQI, IC61C632A-6TQ, IC61C632A-6TQI, IC61C632A-7PQ, IC61C632A-7PQI, IC61C632A-7TQ, IC61C632A-7TQI, IC61C632A-8PQ, IC61C632A-8PQI, IC61C632A-8TQ, IC61C632A-8TQI Datasheet

IC61C632A

BLOCK DIAGRAM

 

 

 

MODE

 

 

 

CLK

CLK

Q0

A0

A0’

 

 

 

 

 

 

 

 

 

 

BINARY

 

 

 

 

 

COUNTER

 

A1’

 

 

ADV

CE

Q1

A1

 

 

32K x 32

 

 

 

 

 

ADSC

 

 

 

 

CLR

 

 

MEMORY

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

ARRAY

 

15

D

Q

13

15

 

 

A14-A0

 

 

 

 

 

ADDRESS

 

 

 

 

 

REGISTER

 

 

 

 

 

CE

 

 

 

 

 

 

CLK

 

 

32

32

 

 

 

 

 

 

GW

D

Q

 

 

 

 

BWE

DQ32-DQ25

 

 

 

 

BW4

BYTE WRITE

 

 

 

 

 

REGISTERS

 

 

 

 

 

CLK

 

 

 

 

 

 

D

Q

 

 

 

 

BW3

DQ24-DQ17

 

 

 

 

BYTE WRITE

 

 

 

 

 

REGISTERS

 

 

 

 

 

CLK

 

 

 

 

 

 

D

Q

 

 

 

 

 

DQ16-DQ9

 

 

 

 

BW2

BYTE WRITE

 

 

 

 

 

REGISTERS

 

 

 

 

 

CLK

 

 

 

 

 

 

D

Q

 

 

 

 

BW1

DQ8-DQ1

 

 

 

 

BYTE WRITE

 

 

 

 

 

REGISTERS

 

 

 

 

 

CLK

 

 

 

 

 

CE1

 

 

 

4

 

 

CE2

D

Q

 

INPUT

OUTPUT

32

CE3

ENABLE

 

 

REGISTERS

REGISTERS

DATA[32:1]

 

 

 

 

OE

 

REGISTER

 

CLK

CLK

 

 

 

 

CE

 

 

 

 

 

 

CLK

 

 

 

 

 

 

D

Q

 

 

 

 

 

ENABLE

 

 

 

 

 

 

DELAY

 

 

 

 

 

 

REGISTER

 

 

 

 

 

CLK

 

 

 

 

 

OE

 

 

 

 

 

 

Integrated Circuit Solution Inc.

3

SSR015-0A 09/13/2001

IC61C632A

PIN CONFIGURATION

100-Pin LQFP and PQFP (Top View)

NC DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24

NC

VCC

NC

GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32

NC

A6

A7

 

CE1

CE2

 

BW4

 

BW3

 

BW2

 

BW1

 

CE3 VCC

GND CLK

 

GW

 

BWE

 

OE

ADSC

ADSP

 

ADV A8

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100 99 98 97

96 95 94 93

92 91 90 89 88 87 86

85 84 83 82 81

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80

NC

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

79

DQ16

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

78

DQ15

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

77

VCCQ

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

76

GNDQ

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75

DQ14

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74

DQ13

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

73

DQ12

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

72

DQ11

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

71

GNDQ

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

VCCQ

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

69

DQ10

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

68

DQ9

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

67

GND

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

66

NC

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

VCC

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

ZZ

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

DQ8

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

DQ7

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

VCCQ

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

GNDQ

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

DQ6

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

DQ5

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

DQ4

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

DQ3

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

GNDQ

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54

VCCQ

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

53

DQ2

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

DQ1

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

NC

31 32 33

34 35 36 37 38 39 40

41 42 43 44 45 46 47 48 49 50

 

MODE

A5 A4

A3

 

A2 A1 A0 NC

 

NC GND

VCC NC NC A10 A11

A12 A13 A14 NC

NC

 

PIN DESCRIPTIONS

A0-A14

Address Inputs

 

 

CLK

Clock

 

 

ADSP

Processor Address Status

 

 

ADSC

Controller Address Status

 

 

ADV

Burst Address Advance

 

 

BW1-BW4

Synchronous Byte Write Enable

 

 

BWE

Byte Write Enable

 

 

GW

Global Write Enable

 

 

CE1, CE2, CE3

Synchronous Chip Enable

 

 

OE

Output Enable

 

 

DQ1-DQ32

Data Input/Output

 

 

ZZ

Sleep Mode

 

 

MODE

Burst Sequence Mode

 

 

VCC

+3.3V Power Supply

 

 

GND

Ground

 

 

VCCQ

Isolated Output Buffer Supply:

 

+3.3V

 

 

GNDQ

Isolated Output Buffer Ground

 

 

4

Integrated Circuit Solution Inc.

 

SSR015-0A 09/13/2001

IC61C632A

TRUTH TABLE

 

ADDRESS

 

 

 

 

 

 

 

 

 

OPERATION

USED

CE1

CE2

CE3

ADSP ADSC

ADV

WRITE

OE

DQ

Deselected, Power-down

None

H

X

X

X

L

X

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

Deselected, Power-down

None

L

L

X

L

X

X

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

Deselected, Power-down

None

L

X

H

L

X

X

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

Deselected, Power-down

None

L

L

X

H

L

X

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

Deselected, Power-down

None

L

X

H

H

L

X

X

X

High-Z

Read Cycle, Begin Burst

External

L

H

L

L

X

X

X

L

Q

Read Cycle, Begin Burst

External

L

H

L

L

X

X

X

H

High-Z

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Begin Burst

External

L

H

L

H

L

X

L

X

D

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

H

L

X

H

L

Q

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

H

L

X

H

H

High-Z

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

X

X

X

H

H

L

H

L

Q

Read Cycle, Continue Burst

Next

X

X

X

H

H

L

H

H

High-Z

Read Cycle, Continue Burst

Next

H

X

X

X

H

L

H

L

Q

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

H

X

X

X

H

L

H

H

High-Z

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

X

X

X

H

H

L

L

X

D

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

H

X

X

X

H

L

L

X

D

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

X

X

X

H

H

H

H

L

Q

Read Cycle, Suspend Burst

Current

X

X

X

H

H

H

H

H

High-Z

Read Cycle, Suspend Burst

Current

H

X

X

X

H

H

H

L

Q

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

H

X

X

X

H

H

H

H

High-Z

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

X

X

X

H

H

H

L

X

D

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

H

X

X

X

H

H

L

X

D

Notes:

1.All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2.Wait states are inserted by suspending burst.

3.X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH.

4.For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time.

5.ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

PARTIAL TRUTH TABLE

FUNCTION

GW

BWE

BW1

BW2

BW3

BW4

 

 

 

 

 

 

 

 

READ

H

H

X

X

X

X

 

READ

H

X

H

H

H

H

 

 

 

 

 

 

 

 

WRITE Byte 1

H

L

L

H

H

H

 

 

 

 

 

 

 

 

WRITE All Bytes

X

L

L

L

L

L

 

 

 

 

 

 

 

 

WRITE All Bytes

L

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Integrated Circuit Solution Inc.

 

 

 

 

5

SSR015-0A 09/13/2001

 

 

 

 

 

 

 

IC61C632A

INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

A1 A0

A1 A0

A1 A0

00

01

10

11

 

 

 

 

01

00

11

10

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

A1’, A0’ = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Parameter

Value

Unit

TBIAS

Temperature Under Bias

–10 to +85

°C

 

 

 

 

TSTG

Storage Temperature

–55 to +150

°C

 

 

 

 

PD

Power Dissipation

1.8

W

 

 

 

 

IOUT

Output Current (per I/O)

100

mA

 

 

 

 

VIN, VOUT

Voltage Relative to GND for I/O Pins

–0.5 to VCCQ + 0.3

V

 

 

 

 

VIN

Voltage Relative to GND for

–0.5 to 5.5

V

 

for Address and Control Inputs

 

 

 

 

 

 

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3.This device contains circuitry that will ensure the output devices are in High-Z at power up.

6

Integrated Circuit Solution Inc.

 

SSR015-0A 09/13/2001

+ 11 hidden pages