ICSI IC61C256AH-10U, IC61C256AH-12J, IC61C256AH-12JI, IC61C256AH-12N, IC61C256AH-12NI Datasheet
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IC61C256AH
Document Title
32K x 8 High Speed SRAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft March 23,2001
0B Revise typo of t
0C Add SOP package type February 18,2002
0D Revise typo of sop size at page 2,9 April 19,2002
HA on page 7 October 18,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. 1
AHSR010-0D 4/19/2002
IC61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times: 10, 12, 15, 20, 25 ns
• Low active power: 400 mW (typical)
• Low standby power
-- 250 µW (typical) CMOS standby
-- 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible interface and outputs
• Single 5V power supply
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC61C256AH is very high-speed, low power, 32,768
word by 8-bit static RAMs. They are fabricated using ICSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IC61C256AH is pin compatible with other 32k x 8 SRAMs
and are available in 28-pin 300mil PDIP, 300mil SOJ, and
8*13.4mm TSOP-1 package, 330 mil SOP.
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
2 Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
IC61C256AH
PIN CONFIGURATION
28-Pin DIP and SOJ and SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTIONS
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
TRUTH TABLE
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1,ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
CECE
OEOE
CE
OE I/O Operation Vcc Current
CECE
OEOE
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc. 3
AHSR010-0D 4/19/2002
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