ICSI IC61C256AH-10U, IC61C256AH-12J, IC61C256AH-12JI, IC61C256AH-12N, IC61C256AH-12NI, IC61C256AH-12T, IC61C256AH-12TI, IC61C256AH-12U, IC61C256AH-12UI, IC61C256AH-20NI, IC61C256AH-20T, IC61C256AH-20TI, IC61C256AH-20U, IC61C256AH-20UI, IC61C256AH-25JI, IC61C256AH-25NI, IC61C256AH-25TI, IC61C256AH-25UI, IC61C256AH-10J, IC61C256AH-10N, IC61C256AH-10T, IC61C256AH-15J, IC61C256AH-15JI, IC61C256AH-15N, IC61C256AH-15NI, IC61C256AH-15T, IC61C256AH-15TI, IC61C256AH-15U, IC61C256AH-20J, IC61C256AH-20JI, IC61C256AH-20N Datasheet
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IC61C256AH
Document Title
32K x 8 High Speed SRAM
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
March 23,2001 |
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0B |
Revise typo of tHA on page 7 |
October 18,2001 |
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0C |
Add SOP package type |
February 18,2002 |
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0D |
Revise typo of sop size at page 2,9 |
April 19,2002 |
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
AHSR010-0D 4/19/2002
IC61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
•High-speed access times: 10, 12, 15, 20, 25 ns
•Low active power: 400 mW (typical)
•Low standby power
--250 W (typical) CMOS standby
--55 mW (typical) TTL standby
•Fully static operation: no clock or refresh required
•TTL compatible interface and outputs
•Single 5V power supply
DESCRIPTION
The ICSI IC61C256AH is very high-speed, low power, 32,768 word by 8-bit static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IC61C256AH is pin compatible with other 32k x 8 SRAMs and are available in 28-pin 300mil PDIP, 300mil SOJ, and 8*13.4mm TSOP-1 package, 330 mil SOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A14 |
DECODER |
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32K X 8 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE |
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CONTROL |
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CIRCUIT |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 |
Integrated Circuit Solution Inc. |
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AHSR010-0D 4/19/2002 |
IC61C256AH
PIN CONFIGURATION |
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PIN CONFIGURATION |
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28-Pin DIP and SOJ and SOP |
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8x13.4mm TSOP-1 |
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A14 |
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28 |
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VCC |
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A10 |
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OE |
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A12 |
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2 |
27 |
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WE |
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A13 |
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A11 |
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20 |
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CE |
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A7 |
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I/O7 |
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A6 |
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25 |
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A8 |
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A9 |
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I/O6 |
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A8 |
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A5 |
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A9 |
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5 |
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A13 |
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I/O5 |
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A4 |
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A11 |
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I/O4 |
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WE |
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A3 |
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VCC |
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I/O3 |
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OE |
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A2 |
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A10 |
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A14 |
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GND |
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A12 |
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I/O2 |
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A1 |
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CE |
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A7 |
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I/O1 |
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I/O7 |
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A0 |
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A6 |
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I/O0 |
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I/O0 |
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I/O6 |
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A5 |
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A0 |
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I/O1 |
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I/O5 |
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A4 |
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A1 |
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I/O2 |
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I/O4 |
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A3 |
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A2 |
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GND |
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I/O3 |
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PIN DESCRIPTIONS
A0-A14 |
Address Inputs |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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Vcc |
Power |
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GND |
Ground |
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TRUTH TABLE
Mode |
WE |
CE |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
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Output Disabled |
H |
L |
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High-Z |
ICC1,ICC2 |
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Read |
H |
L |
L |
DOUT |
ICC1, ICC2 |
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Write |
L |
L |
X |
DIN |
ICC1, ICC2 |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to +7.0 |
V |
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TBIAS |
Temperature Under Bias |
–55 to +125 |
°C |
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
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PD |
Power Dissipation |
1.5 |
W |
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IOUT |
DC Output Current (LOW) |
20 |
mA |
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Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc. |
3 |
AHSR010-0D 4/19/2002