ICSI IC42S16100 User Manual

IC42S16100

Document Title

512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

Revision History

Revision No History Draft Date Remark

0A Initial Draft August 28,2001
0B revise for typo on page 17 January 10,2002
0C Add Pb-free package December 02,2003
0D Add speed grade -5ns June 25,2004

Obselte speed grade -8ns

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

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IC42S16100

Q

Q

Q

Q

M

512K x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM

FEATURES

• Clock frequency: 200, 166, 143 MHz

• Fully synchronous; all signals referenced to a
positive clock edge

• Two banks can be operated simultaneously and
independently

• Dual internal bank controlled by A11 (bank select)

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length
– (1, 2, 4, 8, full page)

• Programmable burst sequence:
Sequential/Interleave

• Auto refresh, self refresh

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write
operations capability

• Burst termination by burst stop and precharge
command

• Byte controlled by LDQM and UDQM

• Package 400mil 50-pin TSOP-2

• Pb(lead)-free package is available

DESCRIPTION

ICSI

's 16Mb Synchronous DRAM IC42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.

PIN CONFIGURATIONS

50-Pin TSOP-2

VCC

I/O0
I/O1

GNDQ

I/O2
I/O3

VCCQ

I/O4
I/O5

GNDQ

I/O6

I/O7
VCCQ
LDQM

WE
CAS
RAS

CS
A11
A10

A0
A1
A2
A3

VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50

GND

49

I/O15

48

I/O14

47

GND

46

I/O13

45

I/O12

44

VCC

43

I/O11

42

I/O10

41

GND

40

I/O9

39

I/O8

38

VCC

37

NC

36

UDQ

35

CLK

34

CKE

33

NC

32

A9

31

A8

30

A7

29

A6

28

A5

27

A4

26

GND

PIN DESCRIPTIONS

A0-A11 Address Input

A0-A10 Row Address Input

A11 Bank Select Address

A0-A7 Column Address Input

I/O0 to I/O15 Data I/O

CLK System Clock Input

CKE Clock Enable

CS Chip Select
RAS Row Address Strobe Command

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

2 Integrated Circuit Solution Inc.

CAS Column Address Strobe Command
WE Write Enable

LDQM Lower Bye, Input/Output Mask

UDQM Upper Bye, Input/Output Mask

Vcc Power

GND Ground

VccQ Power Supply for I/O Pin

GNDQ Ground for I/O Pin

NC No Connection

DR024-0D 06/25/2004

IC42S16100

PIN FUNCTIONS

Pin No. Symbol Type Function (In Detail)

20 to 24 A0-A10 Input Pin A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32 command input and A0-A7 as column address inputs during read or write command

input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automati­cally after the burst access.
These signals become part of the OP CODE during mode register set command
input.

19 A11 Input Pin A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when

high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.

16 CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the

"Command Truth Table" item for details on device commands.

34 CKE Input Pin The CKE input determines whether the CLK input is enabled within the device.

When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode.

35 CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this

device are acquired in synchronization with the rising edge of this pin.

18 CS Input Pin The CS input determines whether command input is enabled within the device.

Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.

2, 3, 5, 6, 8, 9, 11 I/O0 to I/O Pin I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units

12, 39, 40, 42, 43, I/O15 using the LDQM and UDQM pins.

45, 46, 48, 49

14, 36 LDQM, Input Pin LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,

the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre­sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.

17 RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the

"Command Truth Table" item for details on device commands.

15 WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the

"Command Truth Table" item for details on device commands.

7, 13, 38, 44 VCCQ Power Supply Pin VCCQ is the output buffer power supply.

1, 25 VCC Power Supply Pin VCC is the device internal power supply.

4, 10, 41, 47 GNDQ Power Supply Pin GNDQ is the output buffer ground.

26, 50 GND Power Supply Pin GND is the device internal ground.

The CKE is an asynchronous i

nput.

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IC42S16100

C

R
C

A

5

s

FUNCTIONAL BLOCK DIAGRAM

CLK

KE
CS
AS
AS

WE

A11

10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

COMMAND

DECODER

&

CLOCK

GENERATOR

REFRESH

CONTROLLER

REFRESH

COUNTER

ROW

ADDRESS

LATCH

11

MODE

REGISTER

11

SELF

REFRESH

CONTROLLER

MULTIPLEXER

11

8

11

ROW

ADDRESS

BUFFER

COLUMN

ADDRESS LATCH

ROW

ADDRESS

BUFFER

11

COLUMN

BURST COUNTER

11

MEMORY CELL

2048

ARRAY

BANK 0

SENSE AMP I/O GATE

256

COLUMN DECODER

8

ADDRESS BUFFER

2048

256

SENSE AMP I/O GATE

MEMORY CELL

ARRAY

BANK 1

ROW DECODER ROW DECODER

DATA IN

BUFFER

16

DATA OUT

BUFFER

16 16

DQM

16

I/O 0-1

Vcc/VccQ
GND/GNDQ

S16BLK.ep

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IC42S16100

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VCC MAX Maximum Supply Voltage –1.0 to +4.6 V
VCCQ

MAX Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V

VIN Input Voltage –1.0 to +4.6 V
VOUT Output Voltage –1.0 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +150 °C

DC RECOMMENDED OPERATING CONDITIONS

(2)

(At TA = 0 to +70°C)

Symbol Parameter Min. Typ. Max. Unit

VCC, VCCQ Supply Voltage 3.0 3.3 3.6 V

VIH Input High Voltage
VIL Input Low Voltage

(3)

(4)

2.0 — VDD + 0.3 V

-0.3 — +0.8 V

CAPACITANCE CHARACTERISTICS

(1,2)

(At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)

Symbol Parameter Typ. Max. Unit

CIN1 Input Capacitance: A0-A11 — 4 pF
CIN2 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) — 4 pF
CI/O Data Input/Output Capacitance: I/O0-I/O15 — 5 pF

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. All voltages are referenced to GND.

IH (max) = VCCQ + 2.0V with a pulse width ≤ 3 ns.

3. V

IL (min) = GND – 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns.

4. V

Integrated Circuit Solution Inc. 5

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IC42S16100

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current 0V ≤ VIN ≤ VCC, with pins other than –5 5 µA

the tested pin at 0V

IOL Output Leakage Current Output is disabled –10 10 µA

0V ≤ VOUT ≤ VCC

VOH Output High Voltage Level IOUT = –2 mA 2.4 — V
VOL Output Low Voltage Level IOUT = +2 mA — 0.4 V

ICC1 Operating Current

ICC2 Precharge Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN)——2mA

(In Power-Down Mode)

ICC3 Active Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN)——550mA

(In Non Power-Down Mode) — —6 45 mA

ICC4 Operating Current tCK = tCK (MIN) -5 — 150 mA

(In Burst Mode)

ICC5 Auto-Refresh Current tRC = tRC (MIN) -5 — 100 mA

ICC6 Self-Refresh Current CKE ≤ 0.2V — — 1 mA

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for each
memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Icc1 and Icc4 depend on the output load.

(1,2)

One Bank Operation, CAS latency = 3 -5 — 150 mA
Burst Length=1 -6 — 145 mA

tRC ≥ tRC (min.) -7 — 140 mA

IOUT = 0mA

——740mA

(1)

IOUT = 0mA -6 — 140 mA

-7 — 130 mA

-6 — 90 mA

-7 — 80 mA

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IC42S16100

AC CHARACTERISTICS

(1,2,3)

-5 -6 -7

Symbol Parameter Min. Max. Min. Max. Min. Max Units

t

CK3 Clock Cycle Time CAS Latency = 3 5 — 6 — 7 — ns

tCK2 CAS Latency = 2 7 — 8 — 8.6 — ns
tAC3 Access Time From CLK

(4)

CAS Latency = 3 — 4.5 — 5.5 — 6 ns

tAC2 CAS Latency = 2 — 5 — 6 — 6 ns
tCHI CLK HIGH Level Width 2 — 2 — 2.5 — ns
tCL CLK LOW Level Width 2 — 2 — 2.5 — ns
tOH Output Data Hold Time 2 — 2 — 2 — ns
tLZ Output LOW Impedance Time 0 — 0 — 0 — ns
tHZ3 Output HIGH Impedance Time

(5)

CAS Latency = 3 — 4.5 — 5.5 — 6 ns

tHZ2 CAS Latency = 2 — 5 — 6 — 6 ns
tDS Input Data Setup Time 2 — 2 — 2 — ns
tDH Input Data Hold Time 1 — 1 — 1 — ns
tAS Address Setup Time 2 — 2 — 2 — ns
tAH Address Hold Time 1 — 1 — 1 — ns
tCKS CKE Setup Time 2 — 2 — 2 — ns
tCKH CKE Hold Time 1 — 1 — 1 — ns
tCKA CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — 1CLK+3 — ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 2 — 2 — 2 — ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 1 — 1 — 1 — ns
tRC Command Period (REF to REF / ACT to ACT) 50 — 60 — 70 — ns
tRAS Command Period (ACT to PRE) 30 100,000 36 100,000 42 100,000 ns
tRP Command Period (PRE to ACT) 15 — 18 — 21 — ns
tRCD Active Command To Read / Write Command Delay Time 15 — 18 — 21 — ns
tRRD Command Period (ACT [0] to ACT[1]) 10 — 12 — 14 — ns
tDPL Input Data To Precharge 2CLK — 2CLK — 2CLK — ns

Command Delay time

tDAL Input Data To Active / Refresh 2CLK+tRP — 2CLK+tRP — 2CLK+tRP —ns

Command Delay time (During Auto-Precharge)
tT Transition Time 1 10 1 10 1 10 ns
tREF Refresh Cycle Time (4096) — 64 — 64 — 64 ms

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.

2. Measured with t

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
VIL (max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time t
(max.) when the output is in the high impedance state.

T = 1 ns.

IH (min.) and

HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL

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IC42S16100

I

V

O

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

Symbol Parameter -5 -6 -7 Units

— Clock Cycle Time 5 6 7 ns
— Operating Frequency 200 166 143 MHz
tCAC CAS Latency 3 3 3 cycle
tRCD Active Command To Read/Write Command Delay Time 3 3 3 cycle
tRAC RAS Latency (tRCD + tCAC) 6 6 6 cycle
tRC Command Period (REF to REF / ACT to ACT) 10 10 10 cycle
tRAS Command Period (ACT to PRE) 6 6 6 cycle
tRP Command Period (PRE to ACT) 3 3 3 cycle
tRRD Command Period (ACT[0] to ACT [1]) 2 2 2 cycle
tCCD Column Command Delay Time 1 1 1 cycle

(READ, READA, WRIT, WRITA)

tDPL Input Data To Precharge Command Delay Time 2 2 2 cycle
tDAL Input Data To Active/Refresh Command Delay Time 5 5 5 cycle

(During Auto-Precharge)

tRBD Burst Stop Command To Output in HIGH-Z Delay Time 3 3 3 cycle

(Read)

tWBD Burst Stop Command To Input in Invalid Delay Time 0 0 0 cycle

(Write)

tRQL Precharge Command To Output in HIGH-Z Delay Time 3 3 3 cycle

(Read)

tWDL Precharge Command To Input in Invalid Delay Time 0 0 0 cycle

(Write)

tPQL Last Output To Auto-Precharge Start Time (Read) –2 –2 –2 cycle
tQMD DQM To Output Delay Time (Read) 2 2 2 cycle
tDMD DQM To Input Delay Time (Write) 0 0 0 cycle
tMCD Mode Register Set To Command Delay Time 2 2 2 cycle

AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)

Input

2.4V

1.4V

CLK

0.4V

2.4V

INPUT

UTPUT

1.4V

0.4V

Output Load

/O

8 Integrated Circuit Solution Inc.

tCS

tOH

1.4V 1.4V

Z

O

= 50Ω

CHI

t

tCH

30 pF

tCK

tCL

tAC

50 Ω

+1.4

DR024-0D 06/25/2004

IC42S16100

A

A

A

re

COMMANDS

Active Command Read Command

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

HIGH

ROW

ROW

BANK 1

BANK 0

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

HIGH

COLUMN

AUTO PRECHARGE

NO PRECHARGE

BANK 1

BANK 0

Write Command Precharge Command

CLK

CKE

CS

RAS

HIGH

CLK

CKE

CS

RAS

HIGH

(1)

CAS

WE

0-A9

A10

A11

(1)

COLUMN

AUTO PRECHARGE

BANK 1

BANK 0

CAS

WE

A0-A9

A10

A11

BANK 0 AND BANK 1

BANK 0 OR BANK 1NO PRECHARGE

BANK 1

BANK 0

No-Operation Command Device Deselect Command

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

HIGH

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

HIGH

A11

Notes:

1. A8-A9 = Don't Care.

Integrated Circuit Solution Inc. 9

A11

Don’t Ca

DR024-0D 06/25/2004

IC42S16100

re

A

A

A

COMMANDS (cont.)

Mode Register Set Command Auto-Refresh Command

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

HIGH

OP-CODE

OP-CODE

OP-CODE

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

HIGH

Self-Refresh Command Power Down Command

CLK

CKE

CS

RAS

CLK

CKE

CS

RAS

ALL BANKS IDLE

NOP

NOP

CAS

WE

0-A9

A10

A11

CAS

WE

A0-A9

A10

A11

NOP

NOP

Clock Suspend Command Burst Stop Command

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

BANK(S) ACTIVE

NOP

NOP

NOP

NOP

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

HIGH

A11

A11

Don’t Ca

10 Integrated Circuit Solution Inc.

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IC42S16100

Mode Register Set Command

(CS, RAS, CAS, WE = LOW)

The IC42S16100 product incorporates a register that defines
the device operating mode. This command functions as a
data input pin that loads this register from the pins A0 to
A11. When power is first applied, the stipulated power-on
sequence should be executed and then the IC42S16100
should be initialized by executing a mode register set
command.

Note that the mode register set command can be executed
only when both banks are in the idle state (i.e. deactivated).

Another command cannot be executed after a mode
register set command until after the passage of the period
tMCD, which is the period required for mode register set
command execution.

Active Command

(CS, RAS = LOW, CAS, WE= HIGH)

The IC42S16100 includes two banks of 4096 rows each.
This command selects one of the two banks according to
the A11 pin and activates the row selected by the pins A0
to A10.

This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.

Precharge Command

(CS, RAS, WE = LOW, CAS = HIGH)

This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the bank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period tRP, which is the
period required for bank precharging.

This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs

Read Command

(CS, CAS = LOW, RAS, WE = HIGH)

This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.

The selected bank must be activated before executing this
command.

When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11 pin
remains in the activated state after the burst read completes.

Write Command

(CS, CAS, WE = LOW, RAS = HIGH)

When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the I/O pins in the cycle in which this
command.

The selected bank must be activated before executing this
command.

When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remains in the activated state after the burst write completes.

After the input of the last burst write data, the application
must wait for the write recovery period (tDPL, tDAL) to elapse
according to CAS latency.

Auto-Refresh Command

(CS, RAS, CAS = LOW, WE, CKE = HIGH)

This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.

Both banks must be placed in the idle state before executing
this command.

The stipulated period (tRC) is required for a single refresh
operation, and no other commands can be executed
during this period.

The device goes to the idle state after the internal refresh
operation completes.

This command must be executed at least 4096 times every
64 ms.

This command corresponds to CBR auto-refresh in
conventional DRAMs.

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IC42S16100

Self-Refresh Command

(CS, RAS, CAS, CKE = LOW, WE = HIGH)

This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by dropping
the CKE pin from HIGH to LOW. The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The self­refresh operation is terminated by raising the CKE pin from
LOW to HIGH. The next command cannot be executed
until the device internal recovery period (tRC) has elapsed.
After the self-refresh, since it is impossible to determine the
address of the last row to be refreshed, an auto-refresh
should immediately be performed for all addresses (4096
cycles).

Both banks must be placed in the idle state before executing
this command.

Burst Stop Command

(CS, WE, = LOW, RAS, CAS = HIGH)

The command forcibly terminates burst read and write
operations. When this command is executed during a burst
read operation, data output stops after the CAS latency
period has elapsed.

No Operation

(CS, = LOW, RAS, CAS, WE = HIGH)

This command has no effect on the device.

Device Deselect Command

(CS = HIGH)

This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.

Power-Down Command

(CKE = LOW)

When both banks are in the idle (inactive) state, or when at
least one of the banks is not in the idle (inactive) state, this
command can be used to suppress device power dissipation
by reducing device internal operations to the absolute
minimum. Power-down mode is started by dropping the
CKE pin from HIGH to LOW. Power-down mode continues
as long as the CKE pin is held low. All pins other than the
CKE pin are invalid and none of the other commands can
be executed in this mode. The power-down operation is
terminated by raising the CKE pin from LOW to HIGH. The
next command cannot be executed until the recovery
period (t

Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (t
the maximum time that power-down mode can be held is
just under the refresh cycle time.

CKA) has elapsed.

REF). Thus

Clock Suspend

(CKE = LOW)

This command can be used to stop the device internal
clock temporarily during a read or write cycle. Clock
suspend mode is started by dropping the CKE pin from
HIGH to LOW. Clock suspend mode continues as long as
the CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated by
raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tCKA) has elapsed.

Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.

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IC42S16100

COMMAND TRUTH TABLE

(1,2)

CKE

CSCS

RASRAS

CASCAS

Symbol Command n-1 n

(5)

(5,6)

(3,4)

HXLLLLX OP CODE X
H H L L L H X X X X HIGH-Z
HLLLLHXX X XHIGH-Z

MRS Mode Register Set
REF Auto-Refresh
SREF Self-Refresh

CS

CSCS

RAS

RASRAS

WEWE

CAS

WE DQM A11 A10 A9-A0 I/On

CASCAS

WEWE

PRE Precharge Selected Bank H X L L H L X BS L X X
PALL Precharge Both Banks H X L L H L X X H X X
ACT Bank Activate
WRIT Write H X L H L L X BS L Column
WRITA Write With Auto-Precharge
READ Read
READA Read With Auto-Precharge
BST Burst Stop

(7)

(8)

(8)

(8)

(9)

H X L L H H X BS Row Row X

(18)

H X L H L L X BS H Column
H X L H L H X BS L Column
H X L H L H X BS H Column

(18)

(18)

(18)

HXLHHLXXXX X
NOP No Operation H X L H H H X X X X X
DESL Device Deselect H X H XXXXX X X X
SBY Clock Suspend / Standby Mode L XXXXXXX X X X
ENB Data Write / Output Enable H XXXXXL X X X Active
MASK Data Mask / Output Disable H XXXXXHX X X HIGH-Z

X
X
X
X

DQM TRUTH TABLE

(1,2)

CKE DQM

Symbol Command n-1 n UPPER LOWER

ENB Data Write / Output Enable H X L L
MASK Data Mask / Output Disable H X H H
ENBU Upper Byte Data Write / Output Enable H X L X
ENBL Lower Byte Data Write / Output Enable H X X L
MASKU Upper Byte Data Mask / Output Disable H X H X
MASKL Lower Byte Data Mask / Output Disable H X X H

CKE TRUTH TABLE

(1,2)

CKE

CSCS

RASRAS

CASCAS

Symbol Command Current State n-1 n

CS

CSCS

RAS

RASRAS

WEWE

CAS

WE A11 A10 A9-A0

CASCAS

WEWE

SPND Start Clock Suspend Mode Active H L XXXXXXX
— Clock Suspend Other States L L XXXXXXX
— Terminate Clock Suspend Mode Clock Suspend L H XXXXXXX
REF Auto-Refresh Idle H H L L L H X X X
SELF Start Self-Refresh Mode Idle H LLLLHXXX
SELFX Terminate Self-Refresh Mode Self-Refresh L H L H H H X X X

LHHXXXXXX

PDWN Start Power-Down Mode Idle H L L H H H X X X

HLHXXXXXX

— Terminate Power-Down Mode Power-Down L H XXXXXXX

Integrated Circuit Solution Inc. 13

DR024-0D 06/25/2004

IC42S16100

OPERATION COMMAND TABLE

Current State Command Operation

Idle DESL No Operation or Power-Down

NOP No Operation or Power-Down
BST No Operation or Power-Down L H H L X X X
READ / READA Illegal L H L H V V V
WRIT/WRITA Illegal L H L L V V V
ACT Row Active L L H H V V V
PRE/PALL No Operation L L H L V V X
REF/SELF Auto-Refresh or Self-Refresh
MRS Mode Register Set LLLL OP CODE

Row Active DESL No Operation H XXXXXX

NOP No Operation L H H H X X X
BST No Operation L H H L X X X
READ/READA Read Start
WRIT/WRITA Write Start
ACT Illegal
PRE/PALL Precharge
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Read DESL Burst Read Continues, Row Active When Done H XXXXXX

NOP Burst Read Continues, Row Active When Done L H H H X X X
BST Burst Interrupted, Row Active After Interrupt L H H L X X X
READ/READA Burst Interrupted, Read Restart After Interrupt
WRIT/WRITA Burst Interrupted Write Start After Interrupt
ACT Illegal
PRE/PALL Burst Read Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Write DESL Burst Write Continues, Write Recovery When Done H XXXXXX

NOP Burst Write Continues, Write Recovery When Done L H H H X X X
BST Burst Write Interrupted, Row Active After Interrupt L H H L X X X
READ/READA
WRIT/WRITA
ACT Illegal
PRE/PALL Burst Write Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Read With DESL Burst Read Continues, Precharge When Done H XXXXXX
Auto- NOP Burst Read Continues, Precharge When Done L H H H X X X

Precharge BST Illegal L H H L X X X

READ/READA Illegal L H L H V V V
WRIT/WRITA Illegal L H L L V V V
ACT Illegal
PRE/PALL Illegal
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

(1,2)

CSCS

CS

CSCS

(12)

(12)

(13)

(17)

(17)

(10)

(15)

(16)

(11,16)

(10)

Burst Write Interrupted, Read Start After Interrupt
Burst Write Interrupted, Write Restart After Interrupt

(10)

(10)

(10)

(11,16)

(16)

HXXXXXX
LHHHXX X

LLLHXXX

LHLHVVV
LHLLVVV
LLHHVVV
LLHL VVX

LHLHVVV
LHLLVVV
LLHHVVV

LHLHVVV
LHLLVVV
LLHHVVV

LLHHVVV
LLHL VVX

RASRAS

RAS

RASRAS

CASCAS

WEWE

CAS

WE A11 A10 A9-A0

CASCAS

WEWE

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

(18)

14 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

OPERATION COMMAND TABLE

Current State Command Operation

Write With DESL Burst Write Continues, Write Recovery And Precharge H XXXXXX
Auto-Precharge When Done

NOP Burst Write Continues, Write Recovery And Precharge L H H H X X X
BST Illegal L H H L X X X
READ/READA Illegal L H L H V V V
WRIT/WRITA Illegal L H L L V V V
ACT Illegal
PRE/PALL Illegal
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OPCODE

Row Precharge DESL No Operation, Idle State After t

NOP No Operation, Idle State After tRP Has Elapsed L H H H X X X
BST No Operation, Idle State After t
READ/READA Illegal
WRIT/WRITA Illegal
ACT Illegal
PRE/PALL No Operation, Idle State After tRP Has Elapsed
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Immediately DESL No Operation, Row Active After tRCD Has Elapsed H XXXXXX
Following NOP No Operation, Row Active After tRCD Has Elapsed L H H H X X X

Row Active BST No Operation, Row Active After tRCD Has Elapsed L H H L X X X

READ/READA Illegal
WRIT/WRITA Illegal
ACT Illegal
PRE/PALL Illegal
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Write DESL No Operation, Row Active After tDPL Has Elapsed H XXXXXX
Recovery NOP No Operation, Row Active After tDPL Has Elapsed L H H H X X X

BST No Operation, Row Active After tDPL Has Elapsed L H H L X X X
READ/READA Read Start L H L H V V V
WRIT/WRITA Write Restart L H L L V V V
ACT Illegal
PRE/PALL Illegal
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

(1,2)

(10)

(10)

(10)

(10)

(10)

(10)

(10)

(10,14)

(10)

(10)

(10)

CSCS

RASRAS

CASCAS

CS

RAS

CSCS

RASRAS

LLHHVVV

WEWE

CAS

WE A11 A10 A9-A0

CASCAS

WEWE

(18)

(18)

(18)

LLHL VVX

RP Has Elapsed H XXXXXX

RP Has Elapsed L H H L X X X

(18)

(18)

(18)

(18)

(18)

(18)

(10)

LHLHVVV
LHLLVVV
LLHHVVV
LLHL VVX

LHLHVVV
LHLLVVV
LLHHVVV
LLHL VVX

(18)

(18)

LLHHVVV

(18)

LLHL VVX

Integrated Circuit Solution Inc. 15

DR024-0D 06/25/2004

IC42S16100

OPERATION COMMAND TABLE

Current State Command Operation

Write Recovery DESL No Operation, Idle State After t

(1,2)

CSCS

RASRAS

CASCAS

CS

RAS

CSCS

RASRAS

DAL Has Elapsed H XXXXXX

WEWE

CAS

WE A11 A10 A9-A0

CASCAS

WEWE

With Auto- NOP No Operation, Idle State After tDAL Has Elapsed L H H H X X X
Precharge BST No Operation, Idle State After t

READ/READA Illegal
WRIT/WRITA Illegal
ACT Illegal
PRE/PALL Illegal

(10)

(10)

(10)

(10)

DAL Has Elapsed L H H L X X X

LHLHVVV
LHLLVVV
LLHHVVV
LLHL VVX

(18)

(18)

(18)

REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Refresh DESL No Operation, Idle State After tRP Has Elapsed H XXXXXX

NOP No Operation, Idle State After t
BST No Operation, Idle State After t
READ/READA Illegal L H L H V V V
WRIT/WRITA Illegal L H L L V V V
ACT Illegal L L H H V V V

RP Has Elapsed L H H H X X X
RP Has Elapsed L H H L X X X

(18)

(18)

(18)

PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Mode Register DESL No Operation, Idle State After tMCD Has Elapsed H XXXXXX
Set NOP No Operation, Idle State After tMCD Has Elapsed L H H H X X X

BST No Operation, Idle State After tMCD Has Elapsed L H H L X X X
READ/READA Illegal L H L H V V V
WRIT/WRITA Illegal L H L L V V V
ACT Illegal L L H H V V V

(18)

(18)

(18)

PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input

2. All input signals are latched on the rising edge of the CLK signal.

3. Both banks must be placed in the inactive (idle) state in advance.

4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.

5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored.

6. During a self-refresh operation, all pin data (states) other than CKE is ignored.

7. The selected bank must be placed in the inactive (idle) state in advance.

8. The selected bank must be placed in the active state in advance.

9. This command is valid only when the burst length set to full page.

10. This is possible depending on the state of the bank selected by the A11 pin.

11. Time to switch internal busses is required.

12. The IC42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.

13. The IC42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.

14. Possible if t

15. Illegal if t

16. The conditions for burst interruption must be observed. Also note that the IC42S16100 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.

17. Command input becomes possible after the period t
precharged state immediately after the burst operation completes if auto-precharge is selected.

18. A8,A9 = don't care.

RRD is satisfied.

RAS is not satisfied.

RCD has elapsed. Also note that the IC42S16100 will enter the

16 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

CKE RELATED COMMAND TRUTH TABLE

(1)

CKE

CSCS

RASRAS

CASCAS

Current State Operation n-1 n

CS

CSCS

RAS

RASRAS

WEWE

CAS

WE A11 A10 A9-A0

CASCAS

WEWE

Self-Refresh Undefined H XXXXXXXX

Self-Refresh Recovery
Self-Refresh Recovery

(2)

Illegal

(2)

Illegal

(2)

(2)

LHHXXXXXX
LHLHHXXXX
LHLHLXXXX
LHL L XXXXX

Self-Refresh L L XXXXXXX

Self-Refresh Recovery Idle State After t

RC Has Elapsed H H H XXXXXX

Idle State After tRC Has Elapsed H H L H H XXXX
Illegal H H L H L XXXX
Illegal H H L L XXXXX
Power-Down on the Next Cycle H L H XXXXXX
Power-Down on the Next Cycle H L L H H XXXX
Illegal H L L H L XXXX
Illegal H L L L XXXXX
Clock Suspend Termination on the Next Cycle

(2)

LHXXXXXXX

Clock Suspend L L XXXXXXX

Power-Down Undefined H XXXXXXXX

Power-Down Mode Termination, Idle After L H XXXXXXX
That Termination

(2)

Power-Down Mode L L XXXXXXX

Both Banks Idle No Operation H H H XXXXXX

See the Operation Command Table H H L H XXXXX
Bank Active Or Precharge H H L L H XXXX
Auto-Refresh H H L L L H X X X
Mode Register Set H H LLLL OP CODE
See the Operation Command Table H L H XXXXXX
See the Operation Command Table H L L H XXXXX
See the Operation Command Table H L L L H XXXX
Self-Refresh

(3)

HLLLLHXXX
See the Operation Command Table H LLLLL OP CODE
Power-Down Mode

(3)

LXXXXXXXX

Other States See the Operation Command Table H H XXXXXXX

Clock Suspend on the Next Cycle

(4)

HLXXXXXXX
Clock Suspend Termination on the Next Cycle L H XXXXXXX
Clock Suspend Termination on the Next Cycle L L XXXXXXX

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input

2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The
minimum setup time (t

3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.

4. The input must be command defined in the operation command table.

CKA) required before all commands other than mode termination must be satisfied.

Integrated Circuit Solution Inc. 17

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IC42S16100

TWO BANKS OPERATION COMMAND TRUTH TABLE

(1,2)

Previous State Next State

CSCS

RASRAS

CASCAS

Operation

CS

CSCS

RAS

RASRAS

WEWE

CAS

WE A11 A10 A9-A0 BANK 0 BANK 1 BANK 0 BANK 1

CASCAS

WEWE

DESL H XXXXXX Any Any Any Any
NOP L H H H X X X Any Any Any Any
BST L H H L X X X R/W/A I/A A I/A

I I/A I I/A
I/A R/W/A I/A A
I/A I I/A I

READ/READA L H L H H H CA

HHCA
HLCA
HLCA
LHCA
LHCA
LLCA
LLCA

WRIT/WRITA L H L L H H CA

HHCA
HLCA
HLCA
LHCA
LHCA
LLCA
LLCA

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

I/A R/W/A I/A RP

R/W A A RP

I/A R/W/A I/A R

R/W A A R

R/W/A I/A RP I/A

A R/W RP A

R/W/A I/A R I/A

A R/W R A

I/A R/W/A I/A WP

R/W A A WP

I/A R/W/A I/A W

R/W A A W

R/W/A I/A WP I/A

A R/W WP A

R/W/A I/A W I/A

A R/W W A

ACT L L H H H RA RA Any I Any A

L RA RA I Any A Any

PRE/PALL L L H L X H X R/W/A/I I/A I I

X H X I/A R/W/A/I I I
H L X I/A R/W/A/I I/A I
H L X R/W/A/I I/A R/W/A/I I
L L X R/W/A/I I/A I I/A

L L X I/A R/W/A/I I R/W/A/I
REF LLLHXXX II II
MRS LLLL OPCODE I I I I

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column
Address

2. The device state symbols are interpreted as follows:

I Idle (inactive state)
A Row Active State
R Read
W Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State

3. CA: A8,A9 = don't care.

18 Integrated Circuit Solution Inc.

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IC42S16100

P

SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)

SELF

REFRESH

SREF entry

SREF exit

WRIT

CKE_

MODE

REGISTER

MRS

IDLE

REF

SET

CKE_

CKE

ACT

CKE_

CKE

READ

BANK

ACTIVE

READ

READA

BST BST

WRIT

WRITA

WRITE

WRIT

AUTO

REFRESH

IDLE

POWER

DOWN

ACTIVE

POWER

DOWN

READ

READ

CKE_

CLOCK

SUSPEND

OWER APPLIED

CKE

WRITA

CKE_

CKE

WRITE WITH

AUTO

PRECHARGE

POWER ON

Automatic transition following the
completion of command execution.

Transition due to command input.

WRITA

PRE

PRE

PRE

PRE-

CHARGE

READA

PRE

READA

CKE_

READ WITH

AUTO

PRECHARGE

CKE

CKE

CLOCK

SUSPEND

Integrated Circuit Solution Inc. 19

DR024-0D 06/25/2004

IC42S16100

Device Initialization At Power-On

(Power-On Sequence)

As is the case with conventional DRAMs, the IC42S16100
product must be initialized by executing a stipulated power­on sequence after power is applied.

After power is applied and VCC and VCCQ reach their
stipulated voltages, set and hold the CKE and DQM pins
HIGH for 100 µs. Then, execute the precharge command
to precharge both bank. Next, execute the auto-refresh
command twice or more and define the device operation
mode by executing a mode register set command.

The mode register set command can be also set before
auto-refresh command.

Mode Register Settings

The mode register set command sets the mode register.
When this command is executed, pins A0 to A9, A10, and
A11 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four fields as listed in the table below.

Input Pin Field

A11, A10, A9, A8 Mode Options

A6, A5, A4 CAS Latency

A3 Burst Type

A2, A1, A0 Burst Length

Note that the mode register set command can be executed
only when both banks are in the idle (inactive) state. Wait
at least two cycles after executing a mode register set
command before executing the next command.

CASCAS

CAS Latency

CASCAS

During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register set
command. The optimal CAS latency is determined by the
clock frequency and device speed grade (-10/12). See the
"Operating Frequency / Latency Relationships" item for
details on the relationship between the clock frequency
and the CAS latency. See the table on the next page for
details on setting the mode register.

Burst Length

When writing or reading, data can be input or output data
continuously. In these operations, an address is input only
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length field in
the mode register stipulates the number of data items input
or output in sequence. In the IC42S16100 product, a burst
length of 1, 2, 4, 8, or full page can be specified. See the
table on the next page for details on setting the mode
register.

Burst Type

The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
register set command. The IC42S16100 product supports
sequential mode and interleaved mode burst type settings.
See the table on the next page for details on setting the
mode register. See the "Burst Length and Column Address
Sequence" item for details on I/O data orders in these
modes.

Write Mode

Burst write or single write mode is selected by the OP code
(A11, A10, A9) of the mode register.

A burst write operation is enabled by setting the OP code
(A11, A10, A9) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specified by the column address and bank select address
at the write command set cycle.

A single write operation is enabled by setting OP code
(A11, A10, A9) to (0,0,1). In a single write operation, data
is only written to the column address and bank select
address specified by the write command set cycle without
regard to the bust length setting.

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IC42S16100

MODE REGISTER

11109876543210

WRITE MODE LT MODE BT BL

Burst Length 0 0 0 1 1

Burst Type 0 Sequential

Latency Mode 0 0 0 Reserved

Address Bus
Mode Register (Mx)

M2 M1 M0 Sequential Interleaved

001 2 2
010 4 4
011 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved

M3 Type

1 Interleaved

M6 M5 M4

0 0 1 Reserved
010 2
011 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

CASCAS

CAS Latency

CASCAS

M11 M10 M9 M8 M7 Write Mode

00000 Burst Read & Burst Write
00100 Burst Read & Single Write

others Reserved

Integrated Circuit Solution Inc. 21

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IC42S16100

BURST LENGTH AND COLUMN ADDRESS SEQUENCE

Column Address Address Sequence

Burst Length A2 A1 A0 Sequential Interleaved

2 X X 0 0-1 0-1

X X 1 1-0 1-0

4 X 0 0 0-1-2-3 0-1-2-3

X 0 1 1-2-3-0 1-0-3-2
X 1 0 2-3-0-1 2-3-0-1
X 1 1 3-0-1-2 3-2-1-0

8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page n n n Cn, Cn+1, Cn+2 None

(256) Cn+3, Cn+4.....

...Cn-1(Cn+255),

Cn(Cn+256).....

Notes:

1. The burst length in full page mode is 256.

22 Integrated Circuit Solution Inc.

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IC42S16100

BANK SELECT AND PRECHARGE ADDRESS ALLOCATION

Row X0 — Row Address

X1 — Row Address
X2 — Row Address
X3 — Row Address
X4 — Row Address
X5 — Row Address
X6 — Row Address
X7 — Row Address

X8 — Row Address

X9 — Row Address

X10 0 Precharge of the Selected Bank (Precharge Command) Row Address

1 Precharge of Both Banks (Precharge Command) (Active Command)

X11 0 Bank 0 Selected (Precharge and Active Command)

1 Bank 1 Selected (Precharge and Active Command)

Column Y0 — Column Address

Y1 — Column Address
Y2 — Column Address
Y3 — Column Address
Y4 — Column Address
Y5 — Column Address
Y6 — Column Address
Y7 — Column Address
Y8 — Don't Care
Y9 — Don't Care

Y10 0 Auto-Precharge - Disabled

1 Auto-Precharge - Enables

Y11 0 Bank 0 Selected (Read and Write Commands)

1 Bank 1 Selected (Read and Write Commands)

Integrated Circuit Solution Inc. 23

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IC42S16100

C

C

Burst Read

The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding
to this address is output in synchronization with the clock
signal after the CAS latency period. Next, data
to an address generated automatically by the device is
output in synchronization with the clock signal.

The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length

corresponding

CLK

is a full page is an exception. In this case the output buffers
must be set to the high impedance state by executing a
burst stop command.

Note that upper byte and lower byte output data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (t

QMD) is fixed at two,

regardless of the CAS latency setting, when this function
is used.

The selected bank must be set to the active state before
executing this command.

OMMAND

I/O8-I/O15

I/O0-I/O 7

CAS latency = 2, burst length = 4

READ A0

UDQM

LDQM

READ (CA=A, BANK 0) DATA MASK (LOWER BYTE)

t

QMD=2

DATA MASK (UPPER BYTE)

D

Burst Write

The write cycle is started by executing the command. The
address provided during write command execution is used
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.

Next, data is input in other in synchronization with the clock
signal. During this operation, data is written to address
generated automatically by the device. This cycle terminates
automatically after a number of clock cycles determined by
the stipulated burst length. However, the case where the
burst length is a full page is an exception. In this case the
write cycle must be terminated by executing a burst stop
command. The latency for I/O pin data input is zero,

OUT

OUT

A0

A0

D

OUT

A2 D

OUT

A3

HI-Z

OUT

A1D

D

HI-Z

HI-Z

regardless of the CAS latency setting. However, a wait
period (write recovery: tDPL) after the last data input is
required for the device to complete the write operation.

Note that the upper byte and lower byte input data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (tDMD) is fixed at
zero, regardless of the CAS latency setting, when this
function is used.

The selected bank must be set to the active state before
executing this command.

CLK

OMMAND

I/O

WRITE

DIN 0DIN 1DIN 2DIN 3

BURST LENGTH

CAS latency = 2,3, burst length = 4

24 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

C

0

C

Read With Auto-Precharge

The read with auto-precharge command first executes a
burst read operation and then puts the selected bank in the
precharged state automatically. After the precharge com­pletes, the bank goes to the idle state. Thus this command
performs a read command and a precharge command in
a single operation.

During this operation, the delay period (tPQL) between the
last burst data output and the start of the precharge
operation differs depending on the CAS latency setting.

three, the precharge operation starts on two clock cycles
before the last burst data is output (tPQL = –2). Therefore,
the selected bank can be made active after a delay of tRP
from the start position of this precharge operation.

The selected bank must be set to the active state before
executing this command.

The auto-precharge function is invalid if the burst length is
set to full page.

When the CAS latency setting is two, the precharge
operation starts on one clock cycle before the last burst
data is output (tPQL = –1). When the CAS latency setting is

CLK

OMMAND

I/O

READ WITH AUTO-PRECHARGE

CAS latency = 2, burst length = 4

READA 0

(BANK 0)

D

OUT

0D

PRECHARGE START

OUT

CASCAS

CAS Latency 3 2

CASCAS

tPQL –2 –1

ACT 0

t

PQL

1D

OUT

2D

OUT

t

RP

3

CLK

OMMAND

I/O

READ WITH AUTO-PRECHARGE

CAS latency = 3, burst length = 4

READA 0

(BANK 0)

D

OUT

0D

PRECHARGE START

OUT

t

PQL

1D

OUT

2D

t

OUT

RP

3

Integrated Circuit Solution Inc. 25

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ACT

IC42S16100

C

0

C

Write With Auto-Precharge

The write with auto-precharge command first executes a
burst write operation and then puts the selected bank in the
precharged state automatically. After the precharge
completes the bank goes to the idle state. Thus this
command performs a write command and a precharge
command in a single operation.

During this operation, the delay period (tDAL) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
The delay (tDAL) is tRP plus one CLK period. That is, the
precharge operation starts one clock period after the last
burst data input.

CLK

Therefore, the selected bank can be made active after a
delay of tDAL.

The selected bank must be set to the active state before
executing this command.

The auto-precharge function is invalid if the burst length is
set to full page.

CASCAS

CAS Latency 3 2

CASCAS

DAL 1CLK 1CLK

t

+tRP +tRP

OMMAND

I/O

WRITE A0

PRECHARGE START

DIN 0DIN 1DIN 2DIN 3

ACT 0

tRP

WRITE WITH AUTO-PRECHARGE

(BANK 0)

tDAL

CAS latency = 2, burst length = 4

CLK

OMMAND

I/O

WRITE WITH AUTO-PRECHARGE

WRITE A0

PRECHARGE START

DIN 0DIN 1DIN 2DIN 3

tRP

tDAL

(BANK 0)

ACT

CAS latency = 3, burst length = 4

26 Integrated Circuit Solution Inc.

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IC42S16100

C

C

Interval Between Read Command

A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.

CLK

The interval between two read command (t

CCD) must be at

least one clock cycle.

The selected bank must be set to the active state before
executing this command.

OMMAND

I/O

READ A0 READ B0

D

OUT

A0 D

t

CCD

READ (CA=A, BANK 0) READ (CA=B, BANK 0)

CAS latency = 2, burst length = 4

Interval Between Write Command

A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the data
for the previous write command.

CLK

t

CCD

OMMAND

WRITE A0 WRITE B0

OUT

B0 D

OUT

B1

D

OUT

The interval between two write commands (t

B2

D

OUT

B3

CCD) must be

at least one clock cycle.

The selected bank must be set to the active state before
executing this command.

I/O

DIN A0 DIN B0 DIN B1 DIN B2 DIN B3

WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)

CAS latency = 2, burst length = 4

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IC42S16100

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C

re

Interval Between Write and Read Commands

A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.

CLK

t

CCD

OMMAND

WRITE A0 READ B0

The interval (tCCD) between command must be at least one
clock cycle.

The selected bank must be set to the active state before
executing this command.

I/O

DIN A0

D

OUT

B0 D

OUT

B1 D

OUT

B2D

OUT

B3

HI-Z

WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)

CAS latency = 2, burst length = 4

CLK

t

CCD

OMMAND

WRITE A0 READ B0

I/O

DIN A0 D

WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)

CAS latency = 3, burst length = 4

HI-Z

OUT

B0 D

OUT

OUT

B1 D

B2D

OUT

B3

Don’t Ca

28 Integrated Circuit Solution Inc.

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IC42S16100

C

Interval Between Read and Write Commands

A read command can be interrupted and a new write
command executed while the read cycle is in progress, i.
e., before that cycle completes. Data corresponding to the
new write command can be input at the point new write
command is executed. To prevent collision between input
and output data at the I/On pins during this operation, the

CLK

CCD

t

OMMAND

U/LDQM

I/O

READ A0

HI-Z

WRITE B0

DIN B0 DIN B2DIN B1 DIN B3

output data must be masked using the U/LDQM pins. The
interval (tCCD) between these commands must be at least
one clock cycle.

The selected bank must be set to the active state before
executing this command.

READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)

CAS latency = 2, 3, burst length = 4

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IC42S16100

C

C

Precharge

The precharge command sets the bank selected by pin
A11 to the precharged state. This command can be
executed at a time tRAS following the execution of an active
command to the same bank. The selected bank goes to the
idle state at a time tRP following the execution of the
precharge command, and an active command can be
executed again for that bank.

If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.

CLK

OMMAND

I/O

READ A0

D

OUT

A0 D

READ (CA=A, BANK 0) PRECHARGE (BANK 0)

PRE 0

OUT

A1 D

Read Cycle Interruption

Using the Precharge Command

A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tRQL) from the execution of the precharge
command to the completion of the burst output is the clock
cycle of CAS latency.

CASCAS

CAS Latency 3 2

CASCAS

tRQL 32

t

RQL

OUT

A2

HI-Z

CAS latency = 2, burst length = 4

CLK

OMMAND

READ A0

I/O

READ (CA=A, BANK 0) PRECHARGE (BANK 0)

CAS latency = 3, burst length = 4

PRE 0

D

OUT

A0 D

OUT

t

RQL

A1 D

OUT

A2

HI-Z

30 Integrated Circuit Solution Inc.

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C

Write Cycle Interruption Using the

Precharge Command

A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tWDL) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.

To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.

This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.

CLK

COMMAND

WRITE A0

DQM

I/O

DIN A0

IN A1 DIN A2 DIN A3

D

Inversely, to write all the burst data to the device, the
precharge command must be executed after the write data
recovery period (t

DPL) has elapsed. Therefore, the

precharge command must be executed on one clock cycle
that follows the input of the last burst data item.

CASCAS

CAS Latency 3 2

CASCAS

tWDL 00

tDPL 11

t

WDL=0

PRE 0

WRITE (CA=A, BANK 0)

CAS latency = 2, 3, burst length = 4

CLK

OMMAND

I/O

WRITE A0

DIN A0

WRITE (CA=A, BANK 0) PRECHARGE (BANK 0)

CAS latency = 2, 3, burst length = 4

IN A1 DIN A2 DIN A3

D

MASKED BY DQM

PRECHARGE (BANK 0)

t

DPL

PRE 0

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C

Read Cycle (Full Page) Interruption Using

the Burst Stop Command

The IC42S16100 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IC42S16100 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t

RAS max.) following the burst stop

command.

CLK

OMMAND

I/O

CAS latency = 2, burst length = full page

READ A0

READ (CA=A, BANK 0)

D

OUT

A0 D

After the period (tRBD) required for burst data output to stop
following the execution of the burst stop command has
elapsed, the outputs go to the HIGH impedance state. This
period (tRBD) is two clock cycle when the CAS latency is two
and three clock cycle when the CAS latency is three.

CASCAS

CAS Latency 3 2

CASCAS

tRBD 32

t

RBD

BST

OUT

A0 D

OUT

A1 D

BURST STOP

OUT

A2 D

OUT

A3

HI-Z

CLK

t

RBD

D

BST

OUT

A1

D

OUT

A2

D

OUT

A3

HI-Z

OMMAND

I/O

READ A0

D

OUT

A0 D

READ (CA=A, BANK 0) BURST STOP

OUT

A0

CAS latency = 3, burst length = full page

32 Integrated Circuit Solution Inc.

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IC42S16100

C

C

)

re

Write Cycle (Full Page) Interruption Using

the Burst Stop Command

The IC42S16100 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IC42S16100 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command

CLK

OMMAND

I/O

WRITE A0

DIN A0 DIN A1 DIN ADIN A1 DIN A2

READ (CA=A, BANK 0) BURST STOP

CAS latency = 2, 3, burst length = full page

Burst Data Interruption Using the

U/LDQM Pins (Read Cycle)

Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (tQMD) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to
the HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes

must be executed within the ACT to PRE command period
(tRAS max.) following the burst stop command. After the
period (tWBD) required for burst data input to stop following
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (tWBD) is zero clock
cycles, regardless of the CAS latency.

WBD=0

t

BST PRE 0

INVALID DATA

PRECHARGE (BANK 0

t

RP

Don’t Ca

LOW, output is resumed at a time tQMD later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).

Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.

CLK

OMMAND

READ A0

tQMD=2

UDQM

CAS latency = 2, burst length = 4

LDQM

I/O8-I/O15

I/O0-I/O 7

DOUT A0

READ (CA=A, BANK 0) DATA MASK (LOWER BYTE)

DATA MASK (UPPER BYTE)

HI-Z

D

OUT A1DOUT A0

DOUT A2 DOUT A3

HI-Z

HI-Z

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C

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Burst Data Interruption U/LDQM Pins

(Write Cycle)

Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless
of the CAS latency, as soon as one of the U/LDQM pins
goes HIGH, the corresponding externally applied input
data will no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.

The IC42S16100 will revert to accepting input as soon as

CLK

that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a
byte basis with the UDQM pin controlling upper byte input
(pin I/O8 to I/O15) and the LDQM pin controlling the lower
byte input (pins I/O0 to I/O7).

Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, inparticular,
incrementing of the internal burst counter continues.

OMMAND

UDQM

LDQM

I/O8-I/O15

I/O0-I/O7

WRITE (CA=A, BANK 0) DATA MASK (LOWER BYTE)

DATA MASK (UPPER BYTE)

WRITE A0

tDMD=0

DIN A0 DIN A3

CAS latency = 2, burst length = 4

Burst Read and Single Write

The burst read and single write mode is set up using the
mode register set command. During this operation, the
burst read cycle operates normally, but the write cycle only
writes a single data item for each write cycle. The CAS
latency and DQM latency are the same as in normal mode.

DIN A1

DIN A2

DIN A3

Don’t Ca

CLK

OMMAND

I/O

CAS latency = 2, 3

34 Integrated Circuit Solution Inc.

WRITE A0

DIN A0

WRITE (CA=A, BANK 0)

DR024-0D 06/25/2004

IC42S16100

C

C

C

Bank Active Command Interval

When the selected bank is precharged, the period trp has
elapsed and the bank has entered the idle state, the bank
can be activated by executing the active command. If the
other bank is in the idle state at that time, the active
command can be executed for that bank after the period
tRRD has elapsed. At that point both banks will be in the
active state. When a bank active command has been
executed, a precharge command must be executed for

CLK

t

RRD

that bank within the ACT to PRE command period (tRAS
max). Also note that a precharge command cannot be
executed for an active bank before tRAS (min) has elapsed.

After a bank active command has been executed and the
trcd period has elapsed, read write (including auto­precharge) commands can be executed for that bank.

OMMAND

ACT 0 ACT 1

BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 1)

CLK

t

RCD

OMMAND

CAS latency = 3

ACT 0 READ 0

BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 0)

Clock Suspend

When the CKE pin is dropped from HIGH to LOW during a
read or write cycle, the IC42S16100 enters clock suspend
mode on the next CLK rising edge. This command reduces
the device power dissipation by stopping the device internal
clock. Clock suspend mode continues as long as the CKE
pin remains low. In this state, all inputs other than CKE pin
are invalid and no other commands can be executed. Also,
the device internal states are maintained. When the CKE
pin goes from LOW to HIGH clock suspend mode is
terminated on the next CLK rising edge and device operation
resumes.

The next command cannot be executed until the recovery
period (tCKA) has elapsed.

Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus the
maximum time that clock suspend mode can be held is just
under the refresh cycle time.

CLK

CKE

OMMAND

I/O

READ 0

DOUT 0DOUT 1DOUT 2DOUT 3

READ (BANK 0) CLOCK SUSPEND

CAS latency = 2, burst length = 4

Integrated Circuit Solution Inc. 35

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A

d

re

OPERATION TIMING EXAMPLE

Power-On Sequence, Mode Register Set Cycle

T0 T1 T2 T3 T10 T17 T18 T19 T20

CLK

t

CK

CH

AS

BANK 0 & 1

CHI

t

t

t

t

AH

CH

CH

CH

t

CL

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

HIGH

t

CS

HIGH

t

t

t

CS

t

CS

t

CS

t

t

CODE

CODE

AH

ROW

t

AH

ROW

t

AH

BANK 1

t

AS

t

AS

t

AS

CODE

BANK 0

I/O

WAIT TIME

T=100 s

CAS latency = 2, 3

t

t

RP

<

PALL

><

REF

>

RC

REF

t

t

RC

MRS

>

><

MCD

<

ACT

t

RAS

t

RC

><

Undefine
Don’t Ca

36 Integrated Circuit Solution Inc.

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IC42S16100

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3

t

CK

t

CKS

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

ROW

ROW

BANK 1

BANK 0

t

CKS

t

CKH

t

CKA

t

CKA

t

AH

t

AS

t

RP

POWER DOWN MODE

EXIT

POWER DOWN MODE

t

RAS

t

RC

<

ACT

><

SBY

>

<

PRE

>

<

PALL

>

BANK 0 & 1

BANK 0 OR 1

BANK 1
BANK 0

d

re

Power-Down Mode Cycle

CAS latency = 2, 3

Undefine
Don’t Ca

Integrated Circuit Solution Inc. 37

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IC42S16100

A

d

re

Auto-Refresh Cycle

T0 T1 T2 T3 Tl Tm Tn Tn+1

CLK

tCKS

CKE

CS

RAS

CAS

WE

tCK

tCHtCS

tCHI

tCL

tCHtCS

tCHtCS

tCHtCS

0-A9

A10

A11

DQM

I/O

CAS latency = 2, 3

tAHtAS

BANK 0 & 1

tRP

<

PALL><REF>

tRC tRC

tRC

ROW

ROW

BANK 1

BANK 0

tRAS

tRC

<ACT><REF><REF>

Undefine
Don’t Ca

38 Integrated Circuit Solution Inc.

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IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 Tm Tm+2Tm+1 Tn

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 0 & 1

t

CKS

t

CKS

t

CKA

t

CKA

t

RP

SELF REFRESH MODE

EXIT
SELF

REFRESH

t

RC

t

RC

<

REF

>

<

PALL

><

SELF

>

t

CKS

Self-Refresh Cycle

CAS latency = 2, 3

Note 1: A8,A9 = Don't Care.

Undefine
Don’t Ca

Integrated Circuit Solution Inc. 39

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IC42S16100

A

d

re

Read Cycle

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

t

CKE

CKS

t

CS

t
t

t

CS

t

CS

RAS

t

CS

CAS

t

CS

WE

t

AS

0-A9

t

AS

A10

t

AS

A11

DQM

I/O

CAS latency = 2, burst length = 4

CHI

CK

CKA
CH

t

CH

t

CH

t

CH

t

AH

ROW ROW

t

AH

ROW

t

AH

BANK 1

t

RCD

t

RAS

t

RC

<

ACT

><

t

CL

READ

(1)

COLUMN m

BANK 0 AND 1

NO PRE
BANK 1 BANK 1

BANK 0 OR 1

BANK 1

BANK 0BANK 0

t

CS

t

QMD

t

t

CAC

t

AC

LZ

t

AC

t

OH

D

OUT

mD

OUT

>

t

OH

m+1

t

AC

t

CH

BANK 0

t

OH

D

OUT

m+2

PRE

>

<

<

PALL

>

t

AC

t

RQL

t

RP

D

OUT

t

OH

m+3

t

HZ

ROW

BANK 0

<

ACT

>

t

RCD

t

RAS

t

RC

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

40 Integrated Circuit Solution Inc.

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d

re

A

Read Cycle / Auto-Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

tCKS

CKE

CS

RAS

CAS

WE

0-A9

tAS

A10

tAS

A11

DQM

I/O

CAS latency = 2, burst length = 4

tCHI

tCK

tCKA

tCHtCS

ROW ROW

ROW

BANK 1

<ACT><READA>

tCL

tCHtCS

tCHtCS

tCHtCS

tAHtAS

tAH

tAH

tCS

tRCD tCAC
tRAS
tRC

(1)

COLUMN m

AUTO PRE

BANK 1 BANK 1

BANK 0BANK 0

tQMD

tAC

tLZ

tAC

tOH

DOUT mDOUT m+1

tCH

tAC tAC

tOH

DOUT m+2

tOH

tOH

DOUT m+3

tPQL
tRP

tHZ

ROW

BANK 0

<

ACT>

tRCD

tRAS

tRC

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

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d

re

A

Read Cycle / Full Page

T0 T1 T2 T3 T4 T5 T6 T260 T261 T262 T263

CLK

t

t

CKE

CKS

t

CS

t

t

CKA

t

CS

t

CS

RAS

t

CS

CAS

t

CS

WE

t

AS

0-A9

t

AS

A10

t

AS

A11

DQM

I/O

CAS latency = 2, burst length = full page

CK

CH

CHI

t

CH

t

CH

t

CH

t

AH

ROW

t

AH

ROW

t

AH

BANK 0

t

RCD

t

RAS

t

RC

(BANK 0)

<

ACT 0

><

t

CL

READ0

t

CS

>

(1)

COLUMN

NO PRE

BANK 0

t

QMD

t

CAC

(BANK 0)

BANK 0 OR 1

BANK 0

t

CH

t

AC

t

LZ

t

AC

t

OH

D

OUT

0m D

OUT

t

AC

t

OH

0m+1

D

OUT

0m-1

t

OH

t

AC

t

OH

D

OUT

0m D

t

AC

t

RBD

t

OH

OUT

0m+1

t

HZ

t

RP

(BANK 0)

<

BST

><

PRE 0

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

42 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 0 BANK 0

BANK 0

BANK 0

BANK 1

BANK 1

BANK 1

BANK 0 OR 1 BANK 0 OR 1NO PRE

NO PRE

t

CH

t

AH

t

AS

t

QMD

t

CS

t

AC

t

AC

t

AC

t

AC

t

RCD

(BANK 0)

t

RAS

(BANK 0)

<

ACT 0

>

<

ACT 0

><

ACT1

>

<

READ 0

>

<

READA 0

><

READA 1

>

<

READ 1

><

PRE 0

><

PRE 1

>

t

AH

t

AS

t

CKS

t

CKA

ROW

ROW

ROW

ROW

ROW

COLUMN COLUMN

AUTO PRE AUTO PRE

ROW

t

LZ

t

LZ

t

RCD

(BANK 1)

t

RAS

(BANK 1)

t

RC

(BANK 1)

t

CAC

(BANK 1)

t

CAC

(BANK 1)

t

RC

(BANK 0)

t

RP

(BANK 0)

t

RP

(BANK1)

t

RCD

(BANK 0)

t

RAS

(BANK 0)

t

RC

(BANK 0)

t

RRD

(BANK 0 TO 1)

t

OH

t

OH

t

OH

t

OH

t

HZ

t

HZ

D

OUT

0m D

OUT

0m+1 D

OUT

1m D

OUT

1m+1

(1)(1)

Read Cycle / Ping-Pong Operation (Bank Switching)

CAS latency = 2, burst length = 2

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 43

DR024-0D 06/25/2004

Undefine
Don’t Ca

IC42S16100

d

re

A

Write Cycle

T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10

CLK

t

CKS

CKE

t

CS

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

t
t

t

t

CS

t

CS

t

CS

t

AS

t

t

AS

CHI

CK

CKA
CH

ROW ROW

AS

ROW

BANK 1
BANK 0

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN m

t

AH

BANK 0 AND 1

NO PRE

t

AH

BANK 1

BANK 0 OR 1

BANK 1

t

CS

BANK 0

t

CH

BANK 0

ROW

BANK 1

BANK 0

t

DH

t

DS

t

DH

IN

m+2

D

D

IN

m+3

t

DPL

<

PRE

<

PALL

t

RCD

t

RP

>

<

ACT

><

t

RAS

t

RC

>

Undefine
Don’t Ca

I/O

t

RCD

t

RAS

t

RC

ACT

><

CAS latency = 2, burst length = 4

t

DS

DIN m

WRIT

t

DS

t

DH

D

t

IN

m+1

DH

t

DS

>

Note 1: A8,A9 = Don't Care.

44 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 1
BANK 0

AUTO PRE

t

CH

t

AH

t

AS

t

CS

t

DS

t

DS

t

DS

t

DS

t

DH

t

RAS

t

RC

<

ACT

><

ACT

><

WRITA

>

t

AH

t

AS

t

CKS

t

CKA

ROW ROW

ROW

COLUMN m

ROW

t

RCD

t

DH

t

DH

t

DH

t

RP

t

DAL

t

RCD

t

RAS

t

RC

DIN m

D

IN

m+2

D

IN

m+1

D

IN

m+3

BANK 1

BANK 0

BANK 1

BANK 0

(1)

Write Cycle / Auto-Precharge

CAS latency = 2, burst length = 4

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 45

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Full Page

T0 T1 T2 T3 T4 T5 T259T258 T260 T261 T262

CLK

t

CK

CKA

CH

CHI

ROW

ROW

BANK 0

t

t

t

t

t

AH

t

AH

CH

CH

CH

AH

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

t
t

t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

t

CL

t

COLUMN m

NO PRE

BANK 0

CS

(1)

BANK 0 OR 1

BANK 0

t

CH

t

DH

t

IN 0m+2

D

DS

t

DH

DIN 0m-1 DIN 0m

t

DPL

t

RP

<

BST

><

PRE 0

>

Undefine
Don’t Ca

t

DS

I/O

t

RCD

t

RAS

t

RC

<

ACT 0

><

DIN 0m

WRIT0

CAS latency = 2, burst length = full page

t

DH

>

t

DS

t

DH

D

IN 0m+1

t

DS

Note 1: A8,A9 = Don't Care.

46 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 0

BANK 0

BANK 0 BANK 0

BANK 1

BANK 1

BANK 0 OR 1NO PRE

NO PRE

t

CH

t

AH

t

AS

t

CS

t

DS

t

DS

t

RCD

(BANK 0)

t

RAS

(BANK 0)

<

ACT 0

><

ACT 1

>

<

WRIT 0

>

<

WRITA 0

><

WRITA 1

>

<

WRIT 1

><

PRE 0

><

ACT 0

>

t

AH

t

AS

t

CKS

t

CKA

ROW

ROW

ROW

ROW

ROW

COLUMN COLUMN

AUTO PRE

AUTO PRE

ROW

t

RCD

(BANK 1)

t

RAS

(BANK 1)

t

RC

(BANK 1)

t

RC

(BANK 0)

t

RCD

(BANK 0)

t

RP

(BANK 0)

t

RAS

(BANK 0)

t

RC

(BANK 0)

t

RRD

(BANK 0 TO 1)

t

DPL

t

DPL

t

DH

t

DH

t

DS

t

DH

t

DH

DIN 0m

t

DS

t

DS

t

DH

t

DS

t

DH

t

DH

t

DH

t

DS

t

DS

DIN 0m+1 DIN 0m+2 DIN 0m+3 DIN 1m DIN 1m+1 DIN 1m+2 DIN 1m+3

(1) (1)

Write Cycle / Ping-Pong Operation

CAS latency = 2, burst length = 2

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 47

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Page Mode

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

t

CKE

CKS

t

CS

t
t

t

CS

t

CS

RAS

t

CS

CAS

t

CS

WE

t

AS

0-A9

t

AS

A10

t

AS

A11

DQM

I/O

CAS latency = 2, burst length = 2

CHI

CK

CKA
CH

t

CH

t

CH

t

CH

t

AH

ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

t

RCD

t

RAS

t

RC

<

ACT

><

t

CL

(1)

COLUMN m

NO PRE NO PRE
BANK 1

BANK 0

t

CS

READ

t

QMD

t

LZ

t

CAC

>

COLUMN n

BANK 1

BANK 0

t

AC

READ

(1)

COLUMN o
AUTO PRE

NO PRE

BANK 1
BANK 0

t

AC

t

OH

D

OUT

mD

t

CAC

>

t

AC

t

OH

OUT

m+1 D

READ

<

<

READA

(1)

BANK 0 AND 1

BANK 0 OR 1

BANK 1

BANK 0

t

CH

t

AC

t

OH

OUT

nD

t

CAC

><

>

t

AC

t

OH

OUT

n+1 D

<

<

PALL

PRE

t

AC

t

t

OH

OUT

oD

t

RQL

t

RP

OH

OUT

o+1

t

HZ

>

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

48 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 1
BANK 0

BANK 0

BANK 0 BANK 0

BANK 1

BANK 0 OR 1

BANK 0 AND 1

NO PRE

BANK 1

t

QMD

t

AH

t

AS

t

LZ

t

CS

t

RAS

t

RC

<

ACT

><

READ

>

<

READA, ENB

>

<

READ, ENB

><

MASK

>

<

PALL

>

<

PRE

>

t

AH

t

AS

t

CKS

t

CKA

ROW

COLUMN m

COLUMN n

COLUMN o

NO PRE NO PRE

NO PRE

AUTO PRE

ROW

t

CH

t

RCD

t

CAC

t

CAC

t

CAC

t

RQL

t

HZ

t

HZ

t

RP

t

QMD

BANK 1

BANK 0

BANK 1

t

AC

t

LZ

t

AC

t

OH

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

D

OUT

mD

OUT

m+1 D

OUT

nD

OUT

oD

OUT

o+1

(1) (1)

(1)

Read Cycle / Page Mode; Data Masking

CAS latency = 2, burst length = 2

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 49

DR024-0D 06/25/2004

Undefine
Don’t Ca

IC42S16100

d

re

A

Write Cycle / Page Mode

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK

CKA
CH

CHI

ROW

ROW

BANK 1
BANK 0

t

CH

t

CH

t

CH

t

AH

t

AH

t

AH

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

t
t

t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

t

CL

(1)

COLUMN m

NO PRE NO PRE
BANK 1

BANK 0

t

CS

(1) (1)

COLUMN n

BANK 1

BANK 0

COLUMN o
AUTO PRE

NO PRE

BANK 1
BANK 0

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

t

CH

t

I/O

t

RCD

t

RAS

t

RC

<

ACT

><

CAS latency = 2, burst length = 2

t

DS

DIN m

WRIT

DH

t

DIN n

>

DS

IN n+1

D

t

DH

t

DS

t

DH

t

DS

t

DH

DIN m+1

>

WRIT

t

DS

<

WRIT

WRITA

<

DIN o

t

DH

t

DH

t

DS

DIN o+1

t

DPL

t

RP

><

>

<

PALL

<

PRE

>

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

50 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

CK

t

CHI

t

CL

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

CH

t

CS

t

AH

t

AS

BANK 1
BANK 0

BANK 0

BANK 0

BANK 0

BANK 1

BANK 1OR 0

BANK 0 AND 1

BANK 1

t

CH

t

AH

t

AS

t

CS

t

RAS

t

RC

<

ACT

><

WRIT

><

WRIT

>

<

WRITA

>

<

WRIT

><

MASK

>

<

PALL

>

<

PRE

>

t

AH

t

AS

t

CKS

t

CKA

ROW

COLUMN m

COLUMN n

COLUMN o

NO PRE NO PRE

NO PRE

AUTO PRE

ROW

t

RCD

t

DPL

t

RP

BANK 1

BANK 0

BANK 1

t

DS

t

DS

t

DS

t

DH

t

DS

t

DH

t

DH

t

DH

t

DS

t

DH

DIN m

D

IN n

DIN m+1

DIN o

D

IN o+1

(1)

(1)

(1)

Write Cycle / Page Mode; Data Masking

CAS latency = 2, burst length = 2

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 51

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Clock Suspend

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK

CKA

CH

CHI

t

CL

t

CH

t

CH

t

CH

t

AH

ROW ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

t

RCD

t

RAS

t

RC

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

t

CKS

t

CS

t

t

t

t

t

t

t

t

t

CS

CS

CS

AS

AS

AS

COLUMN m

AUTO PRE

NO PRE

BANK 1
BANK 0

t

CS

(1)

t

QMD

t

CAC

t

t

CKS

CKH

BANK 0 AND 1

ROW

BANK 0 OR 1

BANK 1

BANK 1

OUT

m+1

BANK 0

t

OH

t

HZ

t

RP

t

CH

t

AC

t

LZ

t

AC

t

OH

D

OUT

mD

BANK 0

t

RAS

t

RC

<

ACT 0

> <

CAS latency = 2, burst length = 2

READ

<

READ A

>

><

>

PRE

<

PALL

>

ACT

><

>

Undefine
Don’t Ca

<

SPND

><

SPND

Note 1: A8,A9 = Don't Care.

52 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Clock Suspend

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK

CH

CHI

t

t

t

t

CH

CH

CH

AH

t

t

CL

ROW ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

t

t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

t

CKA

CKS

COLUMN m

AUTO PRE

NO PRE

BANK 1

BANK 0

t

CS

(1)

t

CKH

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

t

CH

ROW

BANK 1

BANK 0

t

I/O

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 2, burst length = 2

DS

t

DH

DIN mD

<

SPND

WRIT, SPND

<

WRITA, SPND

>

>

><

t

DS

IN

m+1

t

DPL

t

DH

t

PRE

<

PALL

t

RP

>

>

ACT

RAS

t

RC

><

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 53

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Precharge Termination

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CHI

CK

CKA
CH

ROW ROW

t

t

t

t

CH

CH

CH

t

AH

AH

t

CL

(1)

COLUMN m COLUMN n

ROW

NO PRE

BANK 0 BANK 0

t

CS

BANK 0

t

AH

t

RCD

t

RAS

t

RC

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

t

CKS

t

CS

t

t

t

t

t

t

t

t

t

CS

CS

CS

AS

AS

AS

t

QMD

t

CAC

(1)

AUTO PRE

ROW

BANK 0 OR 1

BANK 1

NO PRE
BANK 1

OUT

t

OH

m+2

t

HZ

BANK 0

t

RCD

t

RAS

t

RC

t

CH

t

AC

t

LZ

t

AC

t

OH

D

OUT

mD

D

OUT

t

OH

m+1

t

AC

t

RQL

t

RP

BANK 0

t

CAC

<

ACT 0

> <

CAS latency = 2, burst length = 4

READ 0

>

><

ACT

><

READ

<

READA

>

>

Undefine
Don’t Ca

<

PRE 0

Note 1: A8,A9 = Don't Care.

54 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Precharge Termination

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CHI

CK

CKA
CH

ROW ROW

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN m COLUMN n

t

AH

ROW

NO PRE

BANK 0 BANK 0

BANK 0

t

t

CS

AH

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

t

t
t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

(1)

AUTO PRE

ROW

BANK 0 OR 1

BANK 1

NO PRE

BANK 1

t

CS

t

t

CH

CH

BANK 0

BANK 0

t

CS

t

WRIT

WRITA

DH

>

>

Undefine
Don’t Ca

I/O

t

RCD

t

RAS

t

RC

<

ACT 0

> <

CAS latency = 2, burst length = 4

t

IN

D

0m+2

DH

t

RCD

t

ACT

RAS

t

RC

><

t

RP

<

PRE 0

><

t

DIN 0m+1

DH

t

DS

t

DH

t

t

DS

DS

DIN 0m DIN 0n

WRIT 0

>

t

DS

<

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 55

DR024-0D 06/25/2004

IC42S16100

d

re

I

Read Cycle / Byte Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK

CH

CHI

ROW

ROW

BANK 1
BANK 0

t

t

CH

t

CH

t

CH

t

AH

t

AH

t

AH

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

UDQM

LDQM

/O8-15

I/O0-7

t

CKS

t

CS

t

t
t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CKA

CL

t

CS

t

CS

(1)

COLUMN m

AUTO PRE

NO PRE

BANK 1
BANK 0

t

QMD

t

QMD

t

t

t

AC

AC

CH

t

t

ROW

BANK 0 AND 1

ROW

BANK 0 OR 1

BANK 1
BANK 1
BANK 0

t

CH

t

D

OUT

t

OH
m+1

AC

t

LZ

t

HZ

LZ

t

OH

D

OUT

m

t

AC

t

D

OUT

OH
m

LZ

D

OUT

t

OH
m+2

t

AC

D

OUT

t

OH
m+3

BANK 0

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 2, burst length = 4

READ

READA

<

t

CAC

<

>

MASKU

>

ENBU, MASKL

>

t

QMD

>

<

MASKL

t

RQL

t

RP

<

PRE

PALL

<

>

>

><

ACT

t

RCD

t

RAS

t

RC

><

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

56 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

I

Write Cycle / Byte Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

CK

CKA
CH

CHI

ROW

ROW

BANK 1

BANK 0

t

CH

t

CH

t

CH

t

AH

t

AH

t

AH

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

UDQM

t

CKS

t

CS

t

t
t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

t

CL

t

COLUMN m

AUTO PRE

NO PRE

BANK 1

BANK 0

CS

(1)

ROW

BANK 0 AND 1

ROW

BANK 0 OR 1

BANK 1

BANK 1

t

CH

BANK 0

BANK 0

t

CS

t

CH

LDQM

t

DH

t

DS

DIN m+1 DIN m+3

t

DS

IN

m+3

>

<

MASK

<

>

ENB

>

t

t

DH

DH

t

DPL

<

PRE

PALL

<

t

RCD

t

RP

>

>

ACT

t

RAS

t

RC

><

Undefine
Don’t Ca

/O8-15

I/O0-7

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 2, burst length = 4

t

DS

t

t

DS

t

DS

<

DH

D

IN

m

t

DH

IN

m D

D

WRIT

>

MASKL

WRITA

<

>

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 57

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle, Write Cycle / Burst Read, Single Write

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

t

t

CKE

CKS

t

CS

t

t

CKA

t

CS

t

CS

RAS

t

CS

CAS

t

CS

WE

t

AS

0-A9

t

AS

A10

t

AS

A11

DQM

I/O

CAS latency = 2, burst length = 4

CK

CH

CHI

ROW

ROW

t

CL

t

CH

t

CH

t

CH

t

AH

(1) (1)

COLUMN m

t

AH

NO PRE

t

AH

BANK 1

BANK 1

BANK 0BANK 0

t

CS

t

RCD

t

RAS

t

RC

<

ACT

><

READ

>

t

QMD

t

CAC

t

LZ

t

AC

t

D

OUT

t

CH

t

OUT

t

OH

m+1

AC

t

AC
OH
mD

D

OUT

t

t

OH

m+2

AC

D

OUT

t

OH

m+3

COLUMN n

AUTO PRE

t

DS

t

HZ

<

NO PRE

BANK 1
BANK 0

D

IN

n

<

WRIT

>

WRITA

>

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

t

DH

t

DPL

<

PRE

>

PALL

>

<

Undefine
Don’t Ca

t

RP

Note 1: A8,A9 = Don't Care.

58 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

CLK

t

t

CKS

CKE

t

CS

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

CAS latency = 3, burst length = 4

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

CHI

t

t

t

t

CH

CH

CH

AH

t

CL

ROW ROW

t

AS

t

AH

ROW

t

t

AS

AH

BANK 1

t

RCD

t

RAS

t

RC

<

ACT

><

(1)

COLUMN m

BANK 0 AND 1

NO PRE

BANK 1 BANK 1

BANK 0 OR 1

ROW

BANK 1

BANK 0BANK 0

READ

BANK 0

t

OUT

t

t

OH
m+1

CH

AC

PRE

<

<

PALL

D

OUT

t

>

>

t

AC

OH

m+2

t

RQL

t

RP

D

OUT

t

OH
m+3

t

HZ

t

CS

t

CAC

t

QMD

t

AC

t

LZ

t

AC

t

OH

D

OUT

mD

>

BANK 0

<

ACT

>

Undefine
Don’t Ca

t

RCD

t

RAS

t

RC

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 59

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Auto-Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

CLK

t

t

t

t

t

CS

t

CS

t

CS

t

AS

CK

CKA
CH

CHI

t

t

t

CH

CH

CH

t

AH

t

CL

ROW

t

AS

t

AH

ROW

t

t

AS

AH

BANK 1

t

RCD

t

RAS

t

RC

<

ACT

><

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

t

CKS

t

CS

(1)

COLUMN

ROW

AUTO PRE

ROW

BANK 1 BANK 1

BANK 0BANK 0

t

CS

t

CAC

t

QMD

t

AC

t

LZ

t

AC

t

OH

D

OUT

mD

t

OUT

t

t

AC
OH
m+1

CH

D

OUT

t

t

OH

m+2

t

AC

PQL

t

RP

D

OUT

t

OH

m+3

t

HZ

BANK 0

t
t

t

<

ACT

READA

>

>

RCD
RAS

RC

Undefine

CAS latency = 3, burst length = 4

Don’t Ca

Note 1: A8,A9 = Don't Care.

60 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Full Page

T0 T1 T2 T3 T4 T5 T6 T7 T8 T262 T263 T264 T265

CLK

t

t

t

t

t

t

t

t

t

t

CS

CS

CS

AS

AS

AS

CK

CKA
CH

CHI

t

CL

t

CH

t

CH

t

CH

t

AH

ROW

t

AH

ROW

t

AH

BANK 0

t

RCD

(BANK 0)

t

RAS

(BANK 0)

t

RC

(BANK 0)

<

ACT 0

><

t

CKS

CKE

t

CS

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

CAS latency = 3, burst length = full page

(1)

COLUMN

NO PRE

BANK 0

t

CS

t

CAC

(BANK 0)

READ0

>

BANK 0 OR 1

BANK 0

t

CH

t

AC

t

LZ

t

AC

t

OH

DOUT 0m DOUT 0m+1

t

OH

t

AC

t

AC

t

OH

DOUT 0m-1

<

BST

DOUT 0m DOUT 0m+1

t

RBD

><

PRE 0

t

AC

t

OH

t

RP

(BANK 0)

>

t

OH

t

HZ

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 61

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Ping Pong Operation (Bank Switching)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

CLK

t

t

CKS

CKE

t

CS

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

CAS latency = 3, burst length = 2

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

t

t

t

t

ROW

t

AH

ROW

t

AH

BANK 0

t

RRD

(BANK 0 TO 1)

t

RCD

(BANK 0)

t

RAS

(BANK 0)

t

(BANK 0)

ACT 0

>

<

CH

CH

CH

AH

RC

t

CL

(1)

COLUMN

ROW

ROW

(1)

COLUMN

AUTO PRE AUTO PRE

ROW

BANK 1

t

RCD

(BANK 1)

<

ACT1

><

<

NO PRE

BANK 0

t

CS

t

CAC

(BANK 0)

READ 0

>

READA 0

><

t

QMD

t

RAS

(BANK 1)

t

RC

(BANK 1)

<

READA 1

BANK 0 OR 1

BANK 1

t

AC

t

LZ

t

CAC

(BANK 1)

READ 1

><

>

BANK 0

t

OH

D

OUT

0m D

PRE 0

><

t

AC

t

RQL

(BANK 0)

t

RP

(BANK 0)

t

AC

t

OH

OUT

0m+1 D

BANK 0 OR 1NO PRE

BANK1

t

CH

PRE 1

t

AC

t

OH

OUT

1m D

t

RP

(BANK1)

>

ROW

BANK 0

t

OH

OUT

1m+1

(BANK 0)
(BANK 0)

(BANK 0)

<

ACT 0

>

t

HZ

t
t

t

RCD
RAS

RC

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

62 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11

t

t

CKS

t

CS

CHI

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

ROW ROW

t

AS

ROW

t

AS

BANK 1
BANK 0

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN

t

AH

BANK 0 AND 1

NO PRE

t

AH

BANK 1

BANK 0 OR 1

BANK 1

t

CS

BANK 0

t

CH

BANK 0

T12

ROW

BANK 1

BANK 0

t

DH

t

I/O

t

RCD

t

RAS

t

RC

ACT

><

CAS latency = 3, burst length = 4

t

DS

DIN m

WRIT

t

DH

>

t

DS

IN

D

t

DH

m+1

t

DS

D

IN

m+2

DS

D

t

IN

m+3

DH

t

DPL

<

PRE

<

PALL

t

RCD

t

RP

>

ACT

<

t

RAS

t

RC

><

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 63

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Auto-Precharge

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10

t

t

CKS

t

CS

CHI

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

ROW ROW

t

AS

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN

t

AH

AUTO PRE

ROW

t

t

AS

AH

BANK 1
BANK 1
BANK 0

t

CS

BANK 0

t

CH

T11 T12

ROW

BANK 1

BANK 0

t

DH

t

I/O

t

RCD

t

RAS

t

RC

ACT

><

CAS latency = 3, burst length = 4

t

DS

t

DIN m

WRITA

DH

>

t

DS

D

IN

t

DH

m+1

t

DS

D

IN

m+2

DS

D

t

IN

m+3

DH

t

DAL

t

RCD

t

RP

<

ACT

><

Undefine
Don’t Ca

t

RAS

t

RC

Note 1: A8,A9 = Don't Care.

64 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Full Page

T0 T1 T2 T3 T4 T5 T259T6 T260 T261 T262 T263 T264

CLK

t

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

ROW

t

ROW

t

BANK 0

t

t

t

t

CH

CH

CH

AH

AH

AH

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

t

CL

(1)

COLUMN

NO PRE

BANK 0 OR 1

t

CS

BANK 0

t

CH

BANK 0

t

DH

t

I/O

t

RCD

t

RAS

t

RC

<

ACT 0

><

CAS latency = 3, burst length = full page

t

DS

t

DIN 0m

WRIT0

DH

>

t

DS

D

IN

0m+1

t

DH

t

DS

IN

D

0m+2

DS

t

DH

IN

0m-1 D

D

IN

0m

t

DPL

<

BST

><

PRE 0

t

RP

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 65

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Ping-Pong Operation (Bank Switching)

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

t

t

t

t

ROW

t

AH

ROW

t

AH

BANK 0

CH

CH

CH

AH

t

CL

(1)

COLUMN

AUTO PRE

ROW

(1)

COLUMN

AUTO PRE

ROW

NO PRE

BANK 0

t

CS

BANK 1

NO PRE

BANK 1

BANK 0 OR 1

BANK 0

T11 T12

ROW

ROW

BANK 1
BANK 0

t

CH

t

DS

I/O

t

RRD

(BANK 0 TO 1)

t

RCD

(BANK 0)

t

RAS

(BANK 0)

t

RC

(BANK 0)

<

ACT 0

><

<

CAS latency = 3, burst length = 4

t

DS

t

DH

DIN 0m

<

WRIT 0

>

WRITA 0

><

t

t

DH

DS

t

DS

t

DH

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DS

t

DH

t

DH

DIN 0m+1 DIN 0m+2 DIN 0m+3 DIN 1m DIN 1m+1 DIN 1m+2 DIN 1m+3

t

DPL

(BANK 0)

<

WRIT 1

WRITA 1

t

RP

(BANK 0)

><

PRE 0

><

>

ACT 1

t

RCD

(BANK 1)

t

RAS

(BANK 1)

t

RC

(BANK 1)

>

ACT 0

>

Undefine
Don’t Ca

t

DPL

t

RCD

t

RAS

t

RC

Note 1: A8,A9 = Don't Care.

66 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Page Mode

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

CHI

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

ROW

t

AS

ROW

t

AS

BANK 1
BANK 0

<

ACT

><

t

CH

t

CH

t

CH

t

AH

t

AH

t

AH

t

RCD

t

RAS

t

RC

t

CL

(1)

COLUMN m

COLUMN n

NO PRE NO PRE
BANK 1

BANK 1

BANK 0

t

t

CAC

READ

>

CS

t

QMD

BANK 0

t

LZ

READ

>

t

AC

t

AC

t

OH

D

OUT

mD

t

CAC

(1)(1)

COLUMN o
AUTO PRE

NO PRE

BANK 1
BANK 0

t

AC

t

OH

OUT

m+1 D

t

CAC

READ

><

<

<

READA

>

t

t

OH

OUT

nD

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

AC

t

OH

OUT

n+1 D

t

RQL

t

PRE

>

<

<

PALL

>

T11 T12

t

CH

t

AC

RP

t

AC

t

OH

OUT

oD

t

OH

OUT

o+1

t

HZ

Undefine

CAS latency = 3, burst length = 2

Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 67

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Page Mode; Data Masking

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

t

t

t

t

t

t

t

CS

CS

CS

AS

AS

t

AS

CK

CKA
CH

CHI

t

CH

t

CH

t

CH

t

ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

AH

t

CL

(1)

COLUMN m

(1)

COLUMN n

(1)

COLUMN o

AUTO PRE

NO PRE NO PRE

NO PRE

BANK 1

t

CS

t

QMD

BANK 1

BANK 0

t

LZ

t

AC

BANK 1
BANK 0

t

t

CH

t

AC

t

OH

D

OUT

mD

QMD

t

AC

t

OH

OUT

m+1 D

t

OUT

OH

nD

t

CKS

t

CS

BANK 0 AND 1

BANK 0 OR 1

BANK 1

BANK 0 BANK 0

t

AC

T11 T12

t

AC

t

t

OH

OUT

oD

OH

OUT

o+1

t

HZ

Undefine
Don’t Ca

t

RCD

t

RAS

t

RC

<

ACT

><

CAS latency = 3, burst length = 2

t

t

CAC

READ

><

CAC

READ

><

READ, MASK

<

<

READA, MASK

t

>

>

CAC

ENB

t

RQL

t

RP

>

PRE

>

<

<

PALL

>

Note 1: A8,A9 = Don't Care.

68 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Page Mode

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

t

CH

t

CH

t

CH

t

AH

ROW

t

AH

ROW

t

AH

BANK 0

t

CL

(1)

COLUMN m

(1) (1)

COLUMN n

COLUMN o
AUTO PRE

NO PRE NO PRE

BANK 1

BANK 1

NO PRE

BANK 1

t

CS

BANK 0

BANK 0

t

CH

BANK 0

T11 T12

BANK 0 AND 1

BANK 0 OR 1

BANK 1

BANK 0

t

I/O

t

RCD

t

RAS

t

RC

<

ACT

><

CAS latency = 3, burst length = 2

t

DS

DIN m

WRIT

t

DH

>

t

DS

t

DH

DIN m+1

DH

t

DS

IN n

D

WRIT

><

MASK

>

t

DS

D

WRIT

<

<

WRITA

IN

t

><

DH

o

>

t

DH

t

DS

D

IN

o+1

t

DPL

t

RP

PRE

>

<
<

PALL

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 69

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Page Mode; Data Masking

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

CLK

t

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

t

t

t

t

ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

CH

CH

CH

AH

t

CL

(1) (1)

COLUMN m

NO PRE NO PRE

BANK 1

BANK 0

t

CS

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

t

CKS

t

CS

BANK 1

BANK 0

t

COLUMN n

CH

BANK 1

BANK 0

(1)

COLUMN o

AUTO PRE

NO PRE

BANK 0 AND 1

BANK 1OR 0

BANK 1

BANK 0

t

DS

I/O

t

RCD

t

RAS

t

RC

<

ACT

><

CAS latency = 3, burst length = 2

t

DS

t

DH

DIN m

WRIT

><

t

DH

DIN m+1

DH

t

DS

IN n

D

WRIT

>

MASK

>

t

DS

WRIT

<

<

WRITA

t

DH

D

IN

o

><

>

t

DH

t

DS

D

IN

o+1

t

DPL

t

RP

PRE

>

<

<

PALL

>

Undefine
Don’t Ca

t

Note 1: A8,A9 = Don't Care.

70 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Clock Suspend

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

t

t

CKS

t

CS

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CHI

ROW

t

ROW

t
BANK 1
BANK 0

t

t

RAS

t

RC

t

CH

t

CH

t

CH

t

AH

AH

AH

RCD

t

t

CL

(1)

CKS

COLUMN m
AUTO PRE

NO PRE

BANK 1
BANK 0

t

CS

t

QMD

t

CAC

t

CH

t

AC

t

LZ

t

AC

t

OH

D

OUT

mD

t

CKH

BANK 0 AND 1

BANK 0 OR 1

OUT

m+1

BANK 1

BANK 0

t

OH

T12

t

HZ

t

RP

<

ACT

><

CAS latency = 3, burst length = 2

READ

<

READ A

>

><

>

PRE

<

PALL

>
>

Undefine
Don’t Ca

<

SPND

><

SPND

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 71

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Clock Suspend

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

CHI

t

t

t

t

CH

CH

CH

AH

t

CL

ROW ROW

t

AS

t

AH

t

CKS

COLUMN m
AUTO PRE

(1)

ROW

t

CS

NO PRE

BANK 1
BANK 0

t

AS

t
BANK 1
BANK 0

AH

t

CKH

t

CH

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

T11 T12

ROW

BANK 1

BANK 0

t

I/O

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 3, burst length = 2

DS

t

DH

DIN mD

<

SPND

WRIT, SPND

WRITA, SPND

<

><

>

>

t

DS

IN

m+1

t

DPL

t

DH

PRE

PALL

<

t

ACT

RAS

t

RC

><

t

RP

>

>

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

72 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle / Precharge Termination

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

CHI

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

ROW ROW

t

AS

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN m

t

AH

ROW

t

AS

t

BANK 0

t

RCD

t

RAS

t

RC

AH

t

CS

NO PRE

BANK 0

t

QMD

t

CAC

t

LZ

BANK 0 OR 1

BANK 0

t

CH

t

AC

t

D

OUT

t

AC
OH
mD

D

t

OUT

t

AC
OH
m+1

t

RQL

t

RP

t

OUT

t

OH

m+2

HZ

T11 T12

ROW

BANK 1

BANK 0

t

RCD

t

RAS

t

RP

<

PRE 0

<

ACT 0

> <

CAS latency = 3, burst length = 4

READ 0

>

>

ACT

><

Undefine
Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 73

DR024-0D 06/25/2004

IC42S16100

d

re

A

Write Cycle / Precharge Termination

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

CHI

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

ROW ROW

t

AS

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN m

t

AH

ROW

t

AS

t

BANK 0

AH

t

CS

NO PRE

BANK 0

t

CH

BANK 0 OR 1

BANK 0

t

CS

t

CH

T11 T12

ROW

BANK 1

BANK 0

t

I/O

t

RCD

t

RAS

t

RC

<

ACT 0

>

CAS latency = 3, burst length = 4

t

DIN 0m+1

DH

t

DS

t

DH

t

DIN 0m

WRIT 0

<

DS

>

t

DS

IN

0m+2

D

DH

<

PRE 0

t

RCD

t

<

ACT

RAS

t

RP

>

Undefine
Don’t Ca

t

RP

>

Note 1: A8,A9 = Don't Care.

74 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

I

Read Cycle / Byte Operation

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

UDQM

LDQM

/O8-15

I/O0-7

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

t

t

CKS

t

CS

t

CK

t

CKA

t

CH

t

CS

t

CS

t

CS

t

AS

CHI

t

t

t

t

CH

CH

CH

AH

t

CL

ROW

t

AS

t

AH

ROW

t

t

AS

AH

BANK 1 BANK 1
BANK 0

(1)

COLUMN m
AUTO PRE

NO PRE

BANK 0

t

CS

t

CS

t

QMD

t

QMD

BANK 0 AND 1

BANK 0 OR 1

BANK 1

OUT

t

t

OH

m+1

AC

t

HZ

t

CH

BANK 0

t

LZ

D

OUT

t

AC

m+2

t

CH

t

AC

t

t

AC

t

t

HZ

LZ

t

OH

D

OUT

m

t

AC

LZ

t

OH

D

OUT

D

m

D

OUT

t

OH

m+3

t

T12

ROW

ROW

BANK 1

BANK 0

HZ

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 3, burst length = 4

READ

<

READA

t

CAC

>

MASKU

<

>

>

t

QMD

ENBU, MASKL

>

MASKL

<

t
t
t

ACT

><

Undefine
Don’t Ca

RCD
RAS
RP

t

RQL

t

RP

<

PRE

<

PALL

>

>

><

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 75

DR024-0D 06/25/2004

IC42S16100

d

re

I

Write Cycle / Byte Operation

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

UDQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

t
t

t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CK

CKA
CH

CHI

t

CH

t

CH

t

CH

t

AH

ROW

t

AH

ROW

t

AH

BANK 1
BANK 0

t

CL

(1)

COLUMN m

AUTO PRE

t

CS

NO PRE

BANK 1

BANK 0

t

CH

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

T12T11

ROW

ROW

BANK 1

BANK 0

t

CS

t

CH

LDQM

t

DH

t

DS

DIN m+1 DIN m+3

t

DS

IN

m+3

MASKL

>

<

MASK

>

ENB

<

t

DH

t

DH

t

DPL

t

RP

<

PRE

>

<

PALL

>

>

t

RCD

t

RAS

t

ACT

><

Undefine
Don’t Ca

RP

/O8-15

I/O0-7

t

RCD

t

RAS

t

RC

<

ACT

> <

CAS latency = 3, burst length = 4

t

DS

t

t

DS

t

DS

DH

D

IN

m

t

DH

D

IN

m D

<

WRIT

>

WRITA

>

<

Note 1: A8,A9 = Don't Care.

76 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

IC42S16100

d

re

A

Read Cycle, Write Cycle / Burst Read, Single Write

CLK

CKE

CS

RAS

CAS

WE

0-A9

A10

A11

DQM

I/O

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

t

CKS

t

CS

t

t

t

t

CS

t

CS

t

CS

t

AS

t

AS

t

AS

CK

CKA

CH

CHI

ROW

ROW

t

CL

t

CH

t

CH

t

CH

t

AH

(1)

COLUMN m

t

AH

NO PRE

t

AH

BANK 1

BANK 1

BANK 0BANK 0

t

CS

t

RC

t

RAS

t

RC

<

ACT

><

READ

t

CAC

>

t

QMD

t

AC

D

OUT

t

LZ

t

AC

t

OH

m

D

OUT

t

OH

m+1

t

HZ

COLUMN n

AUTO PRE

NO PRE

BANK 1
BANK 0

t

DS

D

IN

<

WRIT

WRITA

<

T11 T12

(1)

t

CH

t

DH

n

t

DPL

>

>

BANK 0 AND 1

BANK 0 OR 1

BANK 1
BANK 0

t

RP

<

PRE

>

PALL

>

<

Undefine

CAS latency = 3, burst length = 2

Don’t Ca

Note 1: A8,A9 = Don't Care.

Integrated Circuit Solution Inc. 77

DR024-0D 06/25/2004

IC42S16100

ORDERING INFORMATION
Commercial Range: 0

ORDERING INFORMATION
Industrial Temperature Range: -40

οο

ο

οο

C to 70

Frequency Speed (ns) Order Part No. Package

200MHz 5 IC42S16100-5T 400mil TSOP-2

IC42S16100-5TG 400mil TSOP-2(Pb-free)

166MHz 6 IC42S16100-6T 400mil TSOP-2

IC42S16100-6TG 400mil TSOP-2(Pb-free)

143MHz 7 IC42S16100-7T 400mil TSOP-2

IC42S16100-7TG 400mil TSOP-2(Pb-free)

Frequency Speed (ns) Order Part No. Package

200MHz 5 IC42S16100-5TI 400mil TSOP-2

IC42S16100-5TIG 400mil TSOP-2(Pb-free)

166MHz 6 IC42S16100-6TI 400mil TSOP-2

IC42S16100-6TIG 400mil TSOP-2(Pb-free)

143MHz 7 IC42S16100-7TI 400mil TSOP-2

IC42S16100-7TIG 400mil TSOP-2(Pb-free)

οο

ο

οο

C

οο

ο

οο

C to 85

οο

ο

οο

C

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: [phone]

Fax: [phone]

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: [phone]

FAX: [phone]

http://www.icsi.com.tw

78 Integrated Circuit Solution Inc.

DR024-0D 06/25/2004