ICSI IC41C44002A, IC41C44002ASL, IC41LV44002A, IC41LV44002ASL User Manual

查询IC41C44002A供应商

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

Document Title

4Mx4 bit Dynamic RAM with EDO Page Mode

Revision History

Revision No History Draft Date Remark

0A Initial Draft September 4,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

DR026-0A 09/04/2001

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

4M x 4 (16-MBIT) DYNAMIC RAM

WITH EDO PAGE MODE

FEATURES

• Extended Data-Out (EDO) Page Mode
access cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 2,048 cycles/32 ms

• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply:
5V ± 10% or 3.3V ± 10%

• Self Refresh 2048 cycles for S version

• Low power for L version.

PRODUCT SERIES OVERVIEW

Part No. Refresh Voltage

IS41C44002A 2K 5V ± 10%
IS41C44002AS(L) 2K 5V ± 10%
IS41LV44002A 2K 3.3V ± 10%
IS41LV44002AS(L) 2K 3.3V ± 10%

DESCRIPTION

The ICSI 44002 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 random accesses within a single
row with access cycle time as short as 20 ns per 4-bit word.

These features make the 44002 Series ideally suited for high­bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.

The 44002 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2

KEY TIMING PARAMETERS

Parameter -50 -60 Unit

RAS Access Time (tRAC)5060ns
CAS Access Time (tCAC)1315ns

Column Address Access Time (tAA)2530ns
EDO Page Mode Cycle Time (tPC)2025ns
Read/Write Cycle Time (tRC) 84 104 ns

PIN CONFIGURATION

24 Pin SOJ, TSOP-2

PIN DESCRIPTIONS

24
23
22
21
20
19

18
17
16
15
14
13

GND
I/O3
I/O2
CAS
OE
A9

A8
A7
A6
A5
A4
GND

A0-A10 Address Inputs (2K Refresh)

I/O0-3 Data Inputs/Outputs

WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe

Vcc Power
GND Ground
NC No Connection

DR026-0A 09/04/2001

A0
A1
A2
A3

1
2
3
4
5
6

7
8
9
10
11
12

VCC

I/O0
I/O1

WE

RAS

NC

A10

VCC

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

2 Integrated Circuit Solution Inc.

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

FUNCTIONAL BLOCK DIAGRAM

OE
WE

CAS

RAS

A0-A10

CAS

CONTROL

LOGIC

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS

BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

4,194,304 x 4

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O3

DATA I/O BUFFERS

TRUTH TABLE

Function

RASRAS

RAS

RASRAS

Standby H H X X X High-Z
Read L L H L ROW/COL DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Read-Write L L H→LL→H ROW/COL DOUT, DIN
EDO Page-Mode Read 1st Cycle: L H→L H L ROW/COL DOUT

2nd Cycle: L H→L H L NA/COL DOUT

EDO Page-Mode Write 1st Cycle: L H→L L X ROW/COL DIN

2nd Cycle: L H→L L X NA/COL DIN

EDO Page-Mode 1st Cycle: L H→LH→LL→H ROW/COL DOUT, DIN
Read-Write 2nd Cycle: L H→LH→LL→H NA/COL DOUT, DIN

Hidden Refresh Read L→H→L L H L ROW/COL DOUT

(1)

Write

L→H→L L L X ROW/COL DIN
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh H→L L H X X High-Z

Note:

1. EARLY WRITE only.

Integrated Circuit Solution Inc. 3

DR026-0A 09/04/2001

CASCAS

CAS

CASCAS

WEWE

WE

WEWE

OEOE

OE Address tR/tC I/O

OEOE

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

Functional Description

The IC41C44002A and IC41LV44002A are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
. The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS). RAS is used to latch the first 11 bits
and CAS is used to latch the latter 11 bits.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.

Refresh Cycle

To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:

1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re­freshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before­RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row ad­dresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.
e., 32 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRASS.

The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.

However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 2048 rows must be refreshed
within the average internal refresh rate, prior to the resump­tion of normal operation.

(1)

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial­ization cycles (any combination of cycles containing a
RAS signal).

During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.

Note:

1.Self Refresh is for S version only.

4 Integrated Circuit Solution Inc.

DR026-0A 09/04/2001

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

V

T Voltage on Any Pin Relative to GND 5V −1.0 to +7.0 V

3.3V −0.5 to +4.6

CC Supply Voltage 5V −1.0 to +7.0 V

V

3.3V −0.5 to +4.6
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70

o

C

TSTG Storage Temperature −55 to +125oC

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V

3.3V 3.0 3.3 3.6

VIH Input High Voltage 5V 2.4 − VCC + 1.0 V

3.3V 2.0 − VCC + 0.3

VIL Input Low Voltage 5V −1.0 − 0.8 V

3.3V −0.3 − 0.8

TA Commercial Ambient Temperature 0 − 70

o

C

CAPACITANCE

(1,2)

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A10(A11) 5 pF
CIN2 Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25oC, f = 1 MHz.

Integrated Circuit Solution Inc. 5

DR026-0A 09/04/2001

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

I

IL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc −55µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) −55µA

0V ≤ VOUT ≤ Vcc

VOH Output High Voltage Level IOH = −5.0 mA with VCC=5V 2.4 − V

IOH = −2.0 mA with VCC=3.3V

VOL Output Low Voltage Level IOL = 4.2 mA with VCC=5V − 0.4 V

IOL = 2 mA with VCC=3.3V

ICC1 Standby Current: TTL RAS, CAS ≥ VIH 5V − 2mA

3.3V − 2

ICC2 Standby Current: CMOS RAS, CAS ≥ VCC − 0.2V 5V − 1mA

3.3V − 0.5

ICC3 Operating Current: RAS, CAS, -50 − 120 mA

Random Read/Write

(2,3,4)

Address Cycling, tRC = tRC (min.) -60 − 110

Average Power Supply Current

ICC4 Operating Current: RAS = VIL, CAS, -50 − 90 mA

EDO Page Mode

(2,3,4)

Cycling tPC = tPC (min.) -60 − 80

Average Power Supply Current

ICC5 Refresh Current: RAS, CAS Cycling -50 − 120 mA

(2,3,5)

CBR

tRC = tRC (min.) -6 0 − 110

Average Power Supply Current

ICCS Self Refresh current

(6)

Self Refresh Mode 5V,nromal version 500 µA

5V, L version 350

3.3V, normal version 450

3.3, L version 350

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

CCS is for S version only.

6. I

6 Integrated Circuit Solution Inc.

DR026-0A 09/04/2001