ICS Computers SB686P200, SB686PV200, SB686P5200, SB686PV5200 User Manual

Product Manual
SB686P(V) Series

MANUAL NUMBER : 40110-005-2B

SB686PV5200

SB686P5200

SB686PV200

SB686P200

http://www.indcompsrc.com

6260 SEQUENCE DRIVE, SAN DIEGO, CA 92121-4371 [phone] (FAX) 619-677-0895

INDUSTRIAL COMPUTER SOURCE EUROPE TEL [phone] FAX [phone] • INDUSTRIAL COMPUTER SOURCE (UK) LTD TEL [phone] FAX [phone]

Page - ii

FOREWARD

This product manual provides information to install, operate and or program the referenced product(s)
manufactured or distributed by Industrial Computer Source. The following pages contain information
regarding the warranty and repair policies.

Technical assistance is available at: 1-800-480-0044.

Manual Errors, Omissions and Bugs: A "Bug Sheet" is included as the last page of this manual. Please
use the "Bug Sheet" if you experience any problems with the manual that requires correction.

The information in this document is provided for reference only. Industrial Computer Source does not
assume any liability arising from the application or use of the information or products described herein.
This document may contain or reference information and products protected by copyrights or patents and
does not convey any license under the patent rights of Industrial Computer Source, nor the rights of others.

Copyright © 1997 by Industrial Computer Source, a California Corporation, 6260 Sequence Drive, San
Diego, CA 92121. Industrial Computer Source is a Registered Trademark of Industrial Computer Source.
All trademarks and registered trademarks are the property of their respective owners. All rights reserved.
Printed in the United States of America. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording , or
otherwise, without the prior written permission of the publisher.

Page - iii

Guarantee

A thirty day money-back guarantee is provided on all standard products sold. Special order products are
covered by our Limited Warranty,

however they may not be returned for r efund or credit. EPROMs, RAM,
Flash EPROMs or other forms of solid electronic media are not returnable for credit - but for r eplacement
only. Extended Warranty available. Consult factory.

Refunds

In order to receive refund on a product purchase price, the product must not have been damaged by
the customer or by the common carrier chosen by the customer to return the goods, and the product
must be returned complete (meaning all manuals, software, cables, etc.) within 30 days of receipt
and in as-new and resalable condition. The Return Pr ocedure must be followed to assure prompt
refund.

Restocking Charges

Product returned after 30 days, and before 90 days, of the purchase will be subject to a minimum
20% restocking charge and any charges for damaged or missing parts.

Products not returned within 90 days of purchase, or products which are not in as-new and re­saleable condition, are not eligible for credit return and will be returned to the customer.

Limited Warranty

One-year limited warranty on all products sold with the exception of the “Performance Series” I/O prod­ucts, which are warranted to the original purchaser for as long as they own the product, subject to all other
conditions below, including those regarding neglect, misuse and acts of God. Within one year of purchase,
Industrial Computer Source will repair or replace, at our option, any defective product. At any time after
one year, we will repair or replace, at our option, any defective “Performance Series” I/O product sold.
This does not include products damaged in shipment, or damaged through customer neglect or misuse.
Industrial Computer Source will service the warranty for all standard catalog products for the first year
from the date of shipment. After the first year, for products not manufactured by Industrial Computer
Source, the remainder of the manufacturer's warranty, if any, will be serviced by the manufacturer directly.

The Return Procedure must be followed to assure repair or replacement. Industrial Computer
Source will normally return your replacement or repaired item via UPS Blue. Overnight delivery or

delivery via other carriers is available at additional charge.

The limited warranty is void if the product has been subjected to alteration, neglect, misuse, or
abuse; if any repairs have been attempted by anyone other than Industrial Computer Source or its
authorized agent; or if the failure is caused by accident, acts of God, or other causes beyond the
control of Industrial Computer Source or the manufacturer. Neglect, misuse, and abuse shall include
any installation, operation, or maintenance of the product other than in accordance with the owners’
manual.

No agent, dealer, distributor, service company, or other party is authorized to change, modify, or
extend the terms of this Limited Warranty in any manner whatsoever. Industrial Computer Source
reserves the right to make changes or improvements in any product without incurring any obligation
to similarly alter products previously purchased.

Page - iv

Shipments not in compliance with this Guarantee and
Limited Warranty Return Policy will not be accepted
by Industrial Computer Source.

®

Return Procedure

For any Limited Warranty or Guarantee return, please contact Industrial Computer Source's Customer
Service at 1-800-480-0044 and obtain a Return Material Authorization (RMA) Number. All product(s)
returned to Industrial Computer Source for service or credit must be accompanied by a Return Material
Authorization (RMA) Number. Freight on all returned items must be prepaid by the customer who is
responsible for any loss or damage caused by common carrier in transit. Returns for Warranty must in­clude a Failure Report for each unit, by serial number(s), as well as a copy of the original invoice showing
date of purchase.

To reduce risk of damage, returns of product must be in an Industrial Computer Source shipping
container. If the original container has been lost or damaged, new shipping containers may be
obtained from Industrial Computer Source Customer Service at a nominal cost.

Limitation of Liability

In no event shall Industrial Computer Source be liable for any defect in hardware or software or loss or
inadequacy of data of any kind, or for any direct, indirect, incidental, or consequential damages in connec­tion with or arising out of the performance or use of any product furnished hereunder. Industrial Computer
Source liability shall in no event exceed the purchase price of the product purchased hereunder. The
foregoing limitation of liability shall be equally applicable to any service provided by Industrial Computer
Source or its authorized agent.

Some Sales Items and Customized Systems are not subject to the guarantee and limited warranty. However ,
in these instances any deviations will be disclosed prior to sales and noted in the original invoice. Indus-

trial Computer Source reserves the right to refuse returns or credits on software or special order items.

Page - v

Advisories

Three types of advisories are used throughout the manual to stress important points or warn of potential
hazards to the user or the system. They are the Note, the Caution, and the Warning. Following is an
example of each type of advisory:

Note: The note is used to present special instruction, or to provide extra information which may

help to simplify the use of the product.

CAUTION!

A Caution is used to alert you to a situation which if ignored may cause injury or
damage equipment.

WARNING!

A Warning is used to alert you of a situation which if ignored will cause serious
injury.

Cautions and Warnings are accented with triangular symbols. The exclamation symbol is used in all cau­tions and warnings to help alert you to the important instructions. The lightning flash symbol is used on the
left hand side of a caution or a warning if the advisory relates to the presence of voltage which may be of
sufficient magnitude to cause electrical shock.

Use caution when servicing any electrical component. We have tried to identify the areas which may pose
a Caution or Warning condition in this manual; however, Industrial Computer Source does not claim to
have covered all situations which might require the use of a Caution or Warning.

Y ou must refer to the documentation for any component you install into a computer system to insure proper
precautions and procedures are followed.

Page - vi

Handling Precautions

This product has components which may be damaged by electrostatic discharge. To protect your
processor board from electrostatic damage, be sure to observe the following precautions when
handling or storing the board:

• Keep the processor board in its static-shielded bag until you are ready to perform your
installation.

• Handle the processor board by its edges.

• Do not touch the I/O connector pins.

• Do not apply pressure or attach labels to the processor board.

• Use a grounded wrist strap at your workstation or ground yourself frequently by touching the
metal chassis of the system before handling any components. The system must be plugged into
an outlet that is connected to an earth ground. Use antistatic padding on all work surfaces.

• Avoid static-inducing carpeted areas.

Solder-Side Components

This processor board has components on both sides of the PCB. It is important for you to observe
the following precautions when handling or storing the board to prevent solder-side components
from being damaged or broken off:

• Handle the board only by its edges.

• Store the board in padded shipping material or in an anti-static board rack.

• Do not place an unprotected board on a flat surface.

Page - vii

Table of Contents

FOREWARD .............................................................................................. iii

Guarantee ................................................................................................. iv

Limited Warranty...................................................................................... iv

Return Procedure...................................................................................... v

Limitation of Liability ................................................................................ v

Advisories ................................................................................................. vi

Table of Contents .................................................................................... vii

Chapter 1: Introduction................................................................................................ 1

Models........................................................................................................................................... 1

Features ........................................................................................................................................ 1

How to remain CE Compliant ............................................................................................................... 2

FCC Compliance Statement for FCC Class B Devices ........................................................................ 2

Chapter 2: Configuration & Setup...............................................................................9

Configuration Jumpers .................................................................................................................. 9

Connectors..........................................................................................................................................11

ISA Bus Pin Numbering............................................................................................................... 17

ISA Bus Pin Assignments............................................................................................................ 18

ISA Bus Pin Assignments (continued)......................................................................................... 19

ISA Bus Signal Descriptions........................................................................................................ 20

I/O Address Map ......................................................................................................................... 24

Interrupt Assignments * ............................................................................................................... 25

PCI Local Bus .................................................................................................................................... 26

PCI Overview .............................................................................................................................. 26

PCI Local Bus Signal Definition................................................................................................... 26

PCI Local Bus Pin Numbering ........................................................................................ 27

PCI Local Bus Pin Assignments.................................................................................................. 28

PCI Local Bus Pin Assignments (continued) .................................................................. 29

PCI Local Bus Pin Assignments (continued) .................................................................. 30

PCI Local Bus Signal Descriptions ..................................................................................................... 30

Chapter 3: BIOS Operation........................................................................................ 35

BIOS Errors .................................................................................................................... 37

Running AMBIOS Setup.............................................................................................................. 38

System BIOS Setup Utilities ........................................................................................................ 38

AMIBIOS Setup Main Menu ............................................................................................................... 39

AMIBIOS Setup Main Menu............................................................................................ 39

Auto-Detect Hard Disks............................................................................................................... 41

Change Password ....................................................................................................................... 42

Change Supervisor Password ........................................................................................ 42

Auto Configuration Options ................................................................................................................ 43

Save Settings and Exit ................................................................................................................ 44

Page - viii

Exit Without Saving ..................................................................................................................... 45

Key Conventions ................................................................................................................................ 45

Chapter 4: Standard CMOS Setup ............................................................................ 47

The Standard CMOS Setup Screen.......................................................................................................... 47

Standard CMOS Options ................................................................................................................... 48

Primary and Secondary Hard Disk Drives ...................................................................... 49

Boot Sector Virus Protection .......................................................................................... 53

Saving and Exiting .......................................................................................................... 53

Using a Worksheet for Setup ............................................................................................................. 54

Hard Disk Drive Types.................................................................................................... 54

Chapter 5: Advanced CMOS Setup........................................................................... 56

The Advanced CMOS Setup Screen ........................................................................................................ 56

Advanced CMOS Setup Options........................................................................................................ 57

Quick Boot...................................................................................................................... 57

BootUp Sequence .......................................................................................................... 57

BootUp Num-Lock .......................................................................................................... 58

Floppy Drive Swap.......................................................................................................... 58

Floppy Drive Seek .......................................................................................................... 58

Mouse Support ............................................................................................................... 59

System Keyboard ........................................................................................................... 59

Primary Display .............................................................................................................. 59

Password Check ............................................................................................................ 60

Parity Check ................................................................................................................... 60

OS/2 Compatible Mode .................................................................................................. 60

Wait For ‘F1’ If Error....................................................................................................... 61

Hit ‘DEL’ Message Display.............................................................................................. 61

Internal Cache ................................................................................................................ 61

System BIOS Cacheable................................................................................................ 62

Video or Adapter ROM Shadow ..................................................................................... 62

Saving and Exiting .......................................................................................................... 63

Advanced Chipset Setup.................................................................................................................... 63

The Advanced Chipset Setup Screen....................................................................................................... 63

Advanced Chipset Setup Options....................................................................................................... 64

DRAM Speed (ns) .......................................................................................................... 64

DRAM Integrity Mode (ECC) .......................................................................................... 64

Chapter 6: PCI/Plug and Play Setup .........................................................................71

The PCI / Plug and Play Setup Screen ..................................................................................................... 71

PCI/Plug and Play Setup Options....................................................................................................... 72

Plug and Play Aware O/S ............................................................................................... 72

PCI Latency Timer (PCI Clocks)..................................................................................... 72

PCI IDE BusMaster ........................................................................................................ 73

OffBoard PCI IDE Card .................................................................................................. 73

Page - ix

IRQ5/IRQ9/IRQ10/IRQ11/IRQ15.................................................................................... 74

Chapter 7: Peripheral Setup ...................................................................................... 77

The Peripheral Setup Screen ................................................................................................................... 77

Peripheral Setup Options ................................................................................................................... 77

Appendix A: BIOS Messages .................................................................................... 81

BIOS Beep Codes ....................................................................................................................... 81

BIOS Error Messages ................................................................................................................. 82

ISA BIOS NMI Handler Messages............................................................................................... 86

Port 80 Codes ............................................................................................................................. 86

Additional BUS Checkpoints........................................................................................................ 91

High Byte ........................................................................................................................................... 91

Appendix B: Cirrus Logic 5446 VGA Display Drivers & Utilities ............................93

Introduction ........................................................................................................................................ 93

Utility Software............................................................................................................................. 94

CLMODE ........................................................................................................................ 94

WINMODE...................................................................................................................... 97

Microsoft Windows 3.X .................................................................................................................... 100

Windows NT 3.1 .............................................................................................................................. 104

Windows NT 3.5 .............................................................................................................................. 104

Power Management Screen Saver................................................................................................... 105

Windows 95 ..................................................................................................................................... 107

OS/2 2.1, 2.11, 3.0 ........................................................................................................................... 109

CE Declaration of Conformity

Current Revision 2B

September 1997

Page - x

Chapter 1: Introduction

The SB686P full-featured ISA/PCI processors are single board computers which feature Pentium
(Pro CPU, Intel 440FX (Natoma) chipset, optional Cirrus Logic video interface, DRAM, PCI Lo­cal Bus, cache, floppy controller, dual EIDE interface, PCI Ultra SCSI controller, two serial ports,
parallel port, mouse port, speaker port and keyboard port on a single ISA card.

Models

Model Name CPU Speed

SB686PV5200 Pentium Pro CPU at 200MHz with 512K cache and video interface
SB686P5200 Pentium Pro CPU at 200MHz with 512K cache
SB686PV200 Pentium Pro CPU at 200MHz with 256K cache and video interface
SB686P200 Pentium Pro CPU at 200MHz with 256K cache

Features

• Pentium Pro microprocessor at 200MHz

• Intel Pentium Pro 440FX (Natoma) chipset with PCI bandwidth greater than 100MB/second

• Optional Super VGA on-board video interface with support up to 1280 x 1024 and full-motion
video modes

• DRAM error checking and correction (ECC) support

• 256K or 512K secondary write-back cache memory

• PCI Local Bus supports off-board PCI option cards, on-board PCI Ultra SCSI controller ­Adaptec 7880 and optional Cirrus GD5446 SVGA controller

• Compatible with PCI Industrial Computer Manufacturers Group (PICMG) 2.0 Specification

• Supports up to 256MB of DRAM on-board — EDO or fast page mode

• Floppy drive and dual PCI EIDE drive interface

• Two serial ports and one parallel port

• Automatic or manual peripheral configuration

• Watchdog timer

• Supports 1Mx36, 2Mx36, 4Mx36, 8Mx36 and 16Mx36 SIMMs

• Shadow RAM for System BIOS and peripherals increases system speed and performance

• Full PC compatibility

Manual Number: 40110-005-2 Page 1

How to remain CE Compliant

In order for computer systems to remain CE compliant, only CE compliant parts may be used. To
keep a chassis compliant it must contain only compliant cards, and for cards to remain compliant
they must be used in compliant chassis. Any modifications made to the equipment may affect the
CE compliance standards and should not be done unless approved in writing by Industrial Com­puter Source.

The SB686P (V) is designed to be CE Compliant when used in an CE compliant chassis. Maintain­ing CE Compliance also requires proper cabling techniques. The user is advised to follow proper
cabling techniques from external devices to the interface to ensure a complete CE Compliant sys­tem. Industrial Computer Source does not offer engineering services for designing cabling sys­tems. Although Industrial Computer Source offers accessories, it is the user's responsibility to
ensure they are installed with proper shielding to maintain CE Compliance.

FCC Compliance Statement for FCC Class B Devices

This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions:

(1) This device may not cause harmful interference, and
(2) this device must accept any interference received, including interference that may cause

undesired operation.

This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in accordance with the instructions,
may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful inter­ference to a radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following
measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and the receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver

is connected.

• Consult the dealer or an experienced radio/TV technician for help.

Changes or modifications not expressly approved by the party responsible for compliance could
void the user’s authority to operate the equipment.

Note: The assembler of a personal computer system may be required to test the system and/or

make necessary modifications if a system is found to cause harmful interference or to be
non-compliant with the appropriate standards for its intended use.

Manual Number: 40110-005-2Page 2

ISA BUS

ADDR/DATA

PCI BUS

CNTL

IDE (2)

(DRAM)

Main Memory

PIIX3

CNTL

ECC

DATA

VGA

5446/

1-2MB RAM

DBX

PMC

SCSI

7880

Adaptec

82091

Floppy Serial (2) Parallel

DATA

ADDR

HOST BUS

CNTL

ADDR

PROCESSOR

PENTIUM PRO

Cache

Secondary

Manual Number: 40110-005-2 Page 3

Manual Number: 40110-005-2Page 4

CPU

Intel Pentium Pro at 200MHz using Socket 8

Bus Interfaces

ISA and PCI Local Bus compatible. External 24 mAmp drivers for supporting up to 20-slot
backplanes.

Data Path

DRAM/Memory - 64-bit
ISA Bus - 16-bit
PCI Bus - 32-bit
Video - 64-bit

Bus Speed - ISA

8.25MHz

Bus Speed - PCI

33MHz

DMA Channels

The board is fully PC compatible with seven DMA channels, each supporting type F transfers.

Interrupts

The processor board is fully PC compatible with interrupt steering for PCI plug and play
compatibility.

BIOS (FLASH)

The BIOS is an American Megatrends Hi-Flex AMIBIOS with built-in advanced CMOS setup
for system parameters, peripheral management for configuring on-board peripherals, PCI-to­PCI bridge support and PCI interrupt steering. The BIOS chip is a boot block Flash device ­28F001BX-T120. The BIOS may be upgraded from floppy disk by pressing <Ctrl> + <Home>
immediately after reset or power-up with the floppy disk in drive A:.

Cache Memory

The dedicated internal 64-bit wide non-blocking second level (L2) cache supports 256K or 512K
running at full CPU core speed.

Manual Number: 40110-005-2 Page 5

DRAM Memory

The DRAM interface is a 64-bit path that supports up to 256MB of either Fast Page Mode (FPM)
or Extended Data Out (EDO/Hyper Page Mode) memory. All 256MB is cacheable. The
processor board supports 60ns (optimal) or 70ns industry standard 36-bit wide SIMM DRAM
in four 72-pin SIMM sockets. The DRAM speed is selectable via Advanced Chipset Setup which
is described in the Advanced Setup section of this manual.

The SIMM sockets are arranged in two banks. Bank 0 consists of sockets 1 and 2 (U52 & U53);
bank 1 consists of sockets 3 and 4 (U62 & U63).

Note: T wo SIMMs of the same memory capacity must be used to fill a memory bank. All SIMMs

must have contacts.

The following SIMMs are supported:

1M x 36, 2M x 36, 4M x 36, 8M x 36, 16M x 36

Memory Hole

The processor board supports a 1MB memory hole option at 512KB-640KB or 15MB-16MB.

Error Checking and Correction/Parity

The memory interface includes parity checking and supports ECC mode (via BIOS setting) for
single-error correction, double-error detection and detection of all errors confined to a single
nibble.

Note: ECC is implemented using the eight parity bits available on the two SIMM modules in a

bank. FPM or EDO parity SIMMs must be used for ECC to operate properly.

PCI Local Bus Interface

The processor board is fully compliant with the PCI Local Bus 2.1 Specification. It has optimized
the PCI interface to allow the CPU to sustain the highest possible bandwidth (greater than
100MB/sec sustained) and low latency of the PCI Bus. It supports four PCI masters, pipelined
snoop ahead feature and improved PCI to DRAM write-back policy. The PCI Local Bus
interfaces to the on-board PCI Ultra SCSI controller, the optional Cirrus SVGA controller and
to standard PCI option cards in the backplane. The PCI Local Bus interface to the backplane is
compliant with the PCI Industrial Computer Manufacturers Group (PICMG) 2.0 Specification.

PCI Super VGA Interface (Optional)

The Cirrus Logic GD5446 video interface is a PCI Local Bus device which supports pixel
resolutions up to 1280 x 1024 non-interlaced and 16.8 million colors at resolutions up to 1024
x 768. The processor board provides up to 2MB of on-board EDO display memory with a 64­bit wide data path and 80MHz memory clock. It displays in full-screen, full-motion up to 30
frames per second, true color at 1024 x 768. Independent graphics and video streams can be
displayed on-screen with true-color video and 256-color graphics. Software drivers for
enhanced performance and resolution are available for the most popular operating systems.

Manual Number: 40110-005-2Page 6

PCI Ultra SCSI Interface

The SCSI interface is a PCI Bus Master device which supports Ultra SCSI 16-bit data transfer
up to 40MB per second and bursts data to the host at full PCI speeds. Active termination is
provided with terminator voltage protected by self-resetting fuses. The SCSI controller is an
Adaptec 7880.

PCI Enhanced IDE Interface (DUAL)

A high performance PCI Bus Master EIDE interface is capable of supporting up to four IDE Type
4 disk drives in a master/slave configuration. With LBA settings in the BIOS parameters, disk
drives greater than 528MB are supported. The interface supports transfer rates to 16.7MB per
second.

Floppy Drive Interface

The processor board supports two floppy disk drives. Drives can be 360K to 2.88MB, in any
combination.

Serial Interface

Two high-speed FIFO (16C550) serial ports with independently programmable baud rates are
supported. Each port has BIOS selectable addressing. A filtered connector is provided to
minimize FCC interference.

Enhanced Parallel Interface

The processor board provides a PC/AT compatible bidirectional parallel port and supports
enhanced parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode
is IEEE 1284 compliant. The parallel port has BIOS selectable addressing.

PS/2 Mouse Interface

The processor board provides compatibility with a PS/2-type mouse. The mouse connection can
be made by using either the PS/2 mouse header or the bracket mounted PS/2 mouse mini DIN
connector.

Watchdog Timer

The watchdog timer is a hardware timer which resets the processor board if the timer is not
refreshed by software periodically. The timer is typically used to restart a system in which an
application becomes hung on an external event. When the application is hung, it no longer
refreshes the timer. The watchdog timer then times out and resets the processor board.

The watchdog timer has two levels of enable. First, the watchdog timer jumper must be moved
to the “enabled” position, which puts the watchdog timer under software control.

The second level is done in two phases. First, access to the watchdog timer gate, ADRx, via a
user-defined I/O port must be enabled and configured in registers 3, 8 and 9 of the FDC37C665GT
configuration registers. Bits 7 and 2 of register 3 set ADRx mode, while registers 8 and 9 define
the I/O port address used to write a 0 or 1 to the ADRx bit. The ADRx bit is physically wired
to the gate that is enabled by the jumper.

Manual Number: 40110-005-2 Page 7

Second, the ADRx mode bit must be set to 0, which blocks the clock to the watchdog timer circuit,
thus scheduling a hardware reset in about 1.5 seconds.

Refreshing the watchdog timer consists of the software in the application first toggling the ADRx
bit to 1, thus clearing the watchdog timer delay, and then setting it to 0, which schedules a system
reset in 1.5 seconds.

A set of watchdog timer software code and sample programs are available from Technical
Support.

Power Fail Detection

A hardware reset is issued when on-board voltage drops below 4.75 volts.

Keyboard Interface

The processor board is compatible with an AT type keyboard. The keyboard connection can be
made by using the P5A Combo I/O connector. Keyboard voltage is protected by a self-resetting
fuse.

Battery

A built-in lithium battery is provided, for ten years of data retention for CMOS memory.

Power Requirements

+3.3V @ 700 mAmps typical
+5V @ 6.2 Amps typical
+12V @ < 100 mAmps typical

-12V @ < 100 mAmps typical

Temperature/Environment

Operating Temperature: 0º C. to 60º C.
Storage Temperature: - 40º C. to 70º C.
Humidity Maximum: 90% non-condensing

Mean Time Between Failures (MTBF)

> 75,000 POH (Power-On Hours)

System Performance (Norton SI 32)

200MHz/512K cache - 2.35
200MHz/256K cache - 2.35

Agency Approvals

FCC Conformity with:

47CFR Part 15, Subpart B

CE Conformity with:

EU EMC Directive 89/336/EEC
EU Low Voltage Directive 72/23/EEC

Manual Number: 40110-005-2Page 8

Chapter 2: Configuration & Setup

Configuration Jumpers

The setup of the configuration jumpers on the processor is described below . * indicates the default
value of each jumper.

Note: For two-position jumpers (3-post), “RIGHT” is toward the bracket end of the board; “LEFT”

is toward the memory sockets.

Jumper Description

JU80 CRT Type Select

Install on the TOP for a color CRT. *
Install on the BOTTOM for a monochrome CRT.

JU81 Password Clear

Install for one power-up cycle to reset the password to the default (null
password).

Remove for normal operation. *

JU82 Watchdog Timer

Install on the LEFT for normal reset operation. *
Install on the RIGHT to enable watchdog timer operation.

JU83 CMOS Clear

Install to clear.
Remove to operate. *

JU84 P5A Speaker Connect

Install to connect speaker data signal to pin 8 of the Combo I/O connector
(P5A). *

Remove to disconnect.

JU85 P5A Reset Connect

Install to connect reset data signal to pin 1 of the Combo I/O connector
(P5A). *

Remove to disconnect.

JU86 Interrupt 12 (IRQ12) Select

Install to dedicate IRQ12 to the PS/2 mouse. *
Remove to make IRQ12 available for system use.

Manual Number: 40110-005-2 Page 9

Jumper Description

JU103 Parallel Port DACK

Pins

DACK #7 1-2
DACK #6 3-4
DACK #5 5-6
DACK #3 7-8

JU104 Parallel Port DREQ

Pins

DREQ #7 1-2
DREQ #6 3-4
DREQ #5 5-6
DREQ #3 7-8

JU120 SCSI Termination

Install to disable on-board active termination for the SCSI interface.
Remove to enable active termination. *

JU900 VGA Interrupt Enable (Optional)

Install to enable the VGA interrupt.
Remove to disable the interrupt. *

CPU Speed Jumpers

There are three jumpers (J140, J141 and W99) which must be set correctly to allow the processor
board to take full advantage of the speed of the Pentium CPU. These jumpers must be set as
specified below.

CPU Synthesizer Jumpers Bus Clock
Speed Frequency J140 J141 W99

200MHz 66MHz Out In In

Manual Number: 40110-005-2Page 10

Connectors

Note: Pin 1 on the connectors is indicated by the square pad on the PCB.

P3 - Floppy Drive Connector

34 pin dual row header, Robinson Nugent #IDH-34LP-S3-TR

PIN SIGNAL PIN SIGNAL

1 Gnd 2 N-RPM
3 Gnd 4 NC
5 Gnd 6 D-Rate0
7 Gnd 8 P-Index
9 Gnd 10 N-Motoron 1
11 Gnd 12 N-Drive Sel2
13 Gnd 14 N-Drive Sel1
15 Gnd 16 N-Motoron 2
17 Gnd 18 N-Dir
19 Gnd 20 N-Stop Step
21 Gnd 22 N-Write Data
23 Gnd 24 N-Write Gate
25 Gnd 26 P-Track 0
27 Gnd 28 P-Write Protect
29 Gnd 30 N-Read Data
31 Gnd 32 N-Side Select
33 Gnd 34 Disk Chng

P4A - PS/2 Mouse Header

5 pin single row header, Amp #640456-5

PIN SIGNAL

1 Ms Data
2 Reserved
3 Kbd Gnd
4 Kbd Power (+5V fused) with self-resetting fuse
5 Ms Clock

Manual Number: 40110-005-2 Page 11

P4B - PS/2 Mouse Connector

6 pin mini DIN, Leoco #MDSL06SC00

PIN SIGNAL

1 Ms Data
2 Reserved
3 Gnd
4 Kbd Power (+5V fused) with self-resetting fuse
5 Ms Clock
6 Reserved

P5A - Combo I/O Connector

8 pin single row header, Amp #640456-8

PIN SIGNAL

1 Reset
2 Gnd
3NC
4 Kbd Clock
5 Kbd Data
6 Kbd Lock Data
7 Kbd Power (+5V fused) with self-resetting fuse
8 Speaker Data

P6 - Serial Port 1 Connector

9 pin D, Foxconn International #UDBA11S2LA

PIN SIGNAL PIN SIGNAL

1 Carrier Detect 6 Data Set Ready-I
2 Receive Data-I 7 Request to Send-O
3 Transmit Data-O 8 Clear to Send-I
4 Data Terminal Ready-O 9 Ring Indicator-I
5 Signal Gnd

P7 - Serial Port 2 Connector

10 pin dual row header, Robinson Nugent #IDH-10LP-S3-TR

PIN SIGNAL PIN SIGNAL

1 Carrier Detect 2 Data Set Ready-I
3 Receive Data-I 4 Request to Send-O
5 Transmit Data-O 6 Clear to Send-I
7 Data Terminal Ready-O 8 Ring Indicator-I
9 Signal Gnd 10 NC

Manual Number: 40110-005-2Page 12

P8 - Parallel Port Connector

26 pin dual row header, Robinson Nugent #IDH-26LP-S3-TR

PIN SIGNAL PIN SIGNAL

1 Strobe 2 Auto Feed XT
3 Data Bit 0 4 Error
5 Data Bit 1 6 Init
7 Data Bit 2 8 Slct In
9 Data Bit 3 10 Gnd
11 Data Bit 4 12 Gnd
13 Data Bit 5 14 Gnd
15 Data Bit 6 16 Gnd
17 Data Bit 7 18 Gnd
19 ACK 20 Gnd
21 Busy 22 Gnd
23 Paper End 24 Gnd
25 Slct 26 NC

P9 - CPU Fan

3 pin header, Molex #22-23-2031

PIN SIGNAL

1 Gnd
2 +12V
3NC

P11 - Primary IDE Hard Drive Connector

40 pin dual row header, Robinson Nugent #IDH-40LP-S3-TR

PIN SIGNAL PIN SIGNAL

1 Reset 2 Gnd
3 Data 7 4 Data 8
5 Data 6 6 Data 9
7 Data 5 8 Data 10
9 Data 4 10 Data 11
11 Data 3 12 Data 12
13 Data 2 14 Data 13
15 Data 1 16 Data 14
17 Data 0 18 Data 15
19 Gnd 20 NC
21 DRQ 0 22 Gnd
23 IOW 24 Gnd

Manual Number: 40110-005-2 Page 13

P11 - Primary IDE Hard Drive Connector (cont.)

40 pin dual row header, Robinson Nugent #IDH-40LP-S3-TR

PIN SIGNAL PIN SIGNAL

25 IOR 26 Gnd
27 IORDY 28 +5V
29 DACK 0 30 Gnd
31 IRQ 14 32 IOCS16
33 Add 1 34 NC
35 Add 0 36 Add 2
37 CS 1P 38 CS 3P
39 IDEACTP 40 Gnd

P11A - Secondary IDE Hard Drive Connector

40 pin dual row header, Robinson Nugent #IDH-40LP-S3-TR

PIN SIGNAL PIN SIGNAL

1 Reset 2 Gnd
3 Data 7 4 Data 8
5 Data 6 6 Data 9
7 Data 5 8 Data 10
9 Data 4 10 Data 11
11 Data 3 12 Data 12
13 Data 2 14 Data 13
15 Data 1 16 Data 14
17 Data 0 18 Data 15
19 Gnd 20 NC
21 DRQ 1 22 Gnd
23 IOW 24 Gnd
25 IOR 26 Gnd
27 IORDY 28 +5V
29 DACK 1 30 Gnd
31 MIRQ 0 32 IOCS16
33 Add 1 34 NC
35 Add 0 36 Add 2
37 CS 1S 38 CS 3S
39 IDEACTS 40 Gnd

Manual Number: 40110-005-2Page 14

P12 - Hard Drive LED Connector

4 pin single row header, Amp #640456-4

PIN SIGNAL

1 +5V Pullup
2 LED
3 LED
4 +5V Pullup

P13 - PCI Ultra SCSI Controller Connector

50/68 high density SCSI connector, Amp #749069-7

PIN SIGNAL PIN SIGNAL

1 Gnd 35 SCZDB12
2 Gnd 36 SCZDB13
3 Gnd 37 SCZDB14
4 Gnd 38 SCZDB15
5 Gnd 39 SCZDBPH
6 Gnd 40 SCZDB0
7 Gnd 41 SCZDB1
8 Gnd 42 SCZDB2
9 Gnd 43 SCZDB3
10 Gnd 44 SCZDB4
11 Gnd 45 SCZDB5
12 Gnd 46 SCZDB6
13 Gnd 47 SCZDB7
14 Gnd 48 SCZDBP
15 Gnd 49 Gnd
16 Gnd 50 Gnd
17 TERMPWR 51 TERMPWR
18 TERMPWR 52 TERMPWR
19 NC 53 NC
20 Gnd 54 Gnd
21 Gnd 55 SCZATN
22 Gnd 56 Gnd
23 Gnd 57 SCZBSY
24 Gnd 58 SCZACK
25 Gnd 59 SCZRST
26 Gnd 60 SCZMSG
27 Gnd 61 SCZSEL
28 Gnd 62 SCZCD

Manual Number: 40110-005-2 Page 15

P13 - PCI Ultra SCSI Controller Connector (cont.)

50/68 high density SCSI connector, Amp #749069-7

PIN SIGNAL PIN SIGNAL

29 Gnd 63 SCZREQ
30 Gnd 64 SCZIO
31 Gnd 65 SCZDB8
32 Gnd 66 SCZDB9
33 Gnd 67 SCZDB10
34 WIDEPS 68 SCZDB11

P15 - PCI SVGA Interface Connector (Optional)

15 pin VGA connector, Amp #748390-5

PIN SIGNAL PIN SIGNAL PIN SIGNAL

6 Gnd

1 Red 11 NC

7 Gnd

2 Green 12 EEDI

8 Gnd

3 Blue 13 HSYNC

9 NC

4 NC 14 VSYNC

10 Gnd

5 Gnd 15 EECS

Manual Number: 40110-005-2Page 16

ISA Bus Pin Numbering

Manual Number: 40110-005-2 Page 17

ISA Bus Pin Assignments

The following figures summarize pin assignments for the Industry Standard Architecture (ISA)
Bus connectors.

I/O Pin Signal Name I/O

A1 I OC HK# I
A2 D7 I/O
A3 D6 I/O
A4 D5 I/O
A5 D4 I/O
A6 D3 I/O
A7 D2 I/O
A8 D1 I/O

A9 D0 I/O
A10 CHR DY I
A11 AE N O
A12 SA19 I /O
A13 SA18 I /O
A14 SA17 I /O
A15 SA16 I /O
A16 SA15 I /O
A17 SA14 I /O
A18 SA13 I /O
A19 SA12 I /O
A20 SA11 I /O
A21 SA10 I /O
A22 SA9 I /O
A23 SA8 I /O
A24 SA7 I /O
A25 SA6 I /O
A26 SA5 I /O
A27 SA4 I /O
A28 SA3 I /O
A29 SA2 I /O
A30 SA1 I /O
A31 SA0 I /O

I/O Pin Signal Name I/O

B1 Gnd Ground
B2 RESDRV O
B3 +5V Power
B4 IRQ9 I
B5 -5V Power
B6 DRQ2 I
B7 -12V Power
B8 Gnd I

B9 +12V Power
B10 Gnd Ground
B11 SMWTC# O
B12 SMRDC# O
B13 IOWC# I/O
B14 IORC# I/O
B15 DAK3# O
B16 DRQ3 I
B17 DAK1# O
B18 DRQ1 I
B19 REFRESH# I/O
B20 BCLK O
B21 IRQ7 I
B22 IRQ6 I
B23 IRQ5 I
B24 IRQ4 I
B25 IRQ3 I
B26 DAK2# O
B27 T-C O
B28 BALE O
B29 +5V Power
B30 OSC O
B31 Gnd Ground

Manual Number: 40110-005-2Page 18

ISA Bus Pin Assignments (continued)

I/O P in Sig nal Name I/ O

C1 SBH E# I/ O
C2 LA23 I/O
C3 LA22 I/O
C4 LA21 I/O
C5 LA20 I/O
C6 LA19 I/O
C7 LA18 I/O
C8 LA17 I/O

C9 MRDC # I /O
C10 MW TC# I/O
C11 D8 I/O
C12 D9 I/O
C13 D10 I/O

I/O P in Sig nal Name I/ O

D1 M16# I
D2 IO16# I
D3 IRQ10 I
D4 IRQ11 I
D5 IRQ12 I
D6 IRQ15 I
D7 IRQ14 I
D8 DAK0# O

D9 DRQ0 I
D10 DAK5# O
D11 DRQ5 I
D12 DAK6# O
D13 DRQ6 I

C14 D11 I /O
C15 D12 I/O
C16 D13 I/O
C17 D14 I/O
C18 D15 I/O

D14 DAK7# O
D15 DRQ7 I
D16 +5V Power
D17 Master16# I
D18 Gnd Ground

Manual Number: 40110-005-2 Page 19

ISA Bus Signal Descriptions

The following is a description of the ISA Bus signals. All signal lines are TTL-compatible.

AEN (O)

Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O
channel to allow DMA transfers to take place. When this line is active, the DMA controller has
control of the address bus, the data-bus Read command lines (memory and I/O), and the Write
command lines (memory and I/O)

BALE (O) (Buffered)

Address Latch Enable (BALE) is provided by the bus controller and is used on the system board
to latch valid addresses and memory decodes from the microprocessor. It is available to the I/
O channel as an indicator of a valid microprocessor or DMA address (when used with AEN).
Microprocessor addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced
high during DMA cycles.

BCLK (O)

BCLK is the system clock. The clock has a 50% duty cycle. This signal should only be used
for synchronization. It is not intended for uses requiring a fixed frequency.

CHRDY (I)

I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O device to lengthen
I/O or memory cycles. Any slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command. Machine cycles are extended by an
integral number of clock cycles. This signal should be held low for no more than 2.5
microseconds.

D[15::0] (I/O)

Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor, memory, and I/O
devices. D15 is the most-significant bit and D0 is the least-significant bit. All 8-bit devices on
the I/O channel should use D[7::0] for communications to the microprocessor. The 16-bit
devices will use D[15::0]. To support 8-bit devices, the data on D[15::8] will be gated to D[7::0]
during 8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit devices will be
converted to two 8-bit transfers.

DAK[7::5]#, DAK[3::0]# (O)

DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA requests
DRQ[7::5] and DRQ[3::0]. They are active low.

Manual Number: 40110-005-2Page 20

DRQ[7::5], DRQ[3::0] (I)

DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests used by peripheral
devices and the I/O channel microprocessors to gain DMA service (or control of the system).
They are prioritized, with DRQ0 having the highest priority and DRQ7 having the lowest. A
request is generated by bringing a DRQ line to an active level. A DRQ line must be held high
until the corresponding DMA Request Acknowledge (DAK) line goes active. DRQ[3::0] will
perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers.

IO16# (I)

I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit,
1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be
driven with an open collector or tri-state driver capable of sinking 20 mAmps.

IOCHK# (I)

I/O Channel Check (IOCHK#) provides the system board with parity (error) information about
memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable
system error.

IORC# (I/O)

I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven
by the system microprocessor or DMA controller, or by a microprocessor or DMA controller
resident on the I/O channel. This signal is active low.

IOWC# (I/O)

I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by
any microprocessor or DMA controller in the system. This signal is active low.

IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)

Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor
that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and
IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest
priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from
low to high. The line must be held high until the microprocessor acknowledges the interrupt
request (Interrupt Service routine).

LA[23::17] (I/O)

These signals (unlatched) are used to address memory and I/O devices within the system. They
give the system up to 16MB of addressability. These signals are valid when BALE is high.
LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the
whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling edge of BALE. These signals
also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.

Manual Number: 40110-005-2 Page 21

M16# (I)

M16# Chip Select signals the system board if the present data transfer is a 1wait-state, 16bit,
memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven with
an open collector or tri-state driver capable of sinking 20 mAmps.

Master16# (I)

Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller
on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#.
Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it
to control the system address, data, and control lines (a condition known as tri-state). After
Master16# is low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write command. If this
signal is held low for more than 15microseconds, system memory may be lost because of a lack
of refresh.

NOWS# (I)

The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus
cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit
device without wait cycles, NOWS# is derived from an address decode gated with a Read or
Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait
states, NOWS# should be driven active on system clock after the Read or Write command is
active gated with the address decode for the device. Memory Read and Write commands to a
8-bit device are active on the falling edge of the system clock. NOWS# is active low and should
be driven with an open collector or tristate driver capable of sinking 20 mAmps.

OSC (O)

Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This
signal is not synchronous with the system clock. It has a 50% duty cycle.

REFRESH# (I/O)

The REFRESH# signal is used to indicate a refresh cycle and can be driven by a microprocessor
on the I/O channel.

RESDRV (O)

Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a
low line-voltage outage. This signal is active high.

SA[19::0] (I/O)

Address bits SA[19::0] are used to address memory and I/O devices within the system. These
twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory.
SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge
of BALE. These signals are generated by the microprocessor or DMA Controller. They also may
be driven by other microprocessors or DMA controllers that reside on the I/O channel.

Manual Number: 40110-005-2Page 22

SBHE# (I/O)

System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus,
D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8].

SMRDC# (O), MRDC# (I/O)

These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active
only when the memory decode is within the low 1MB of memory space. MRDC# is active on
all memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in
the system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When
a microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid
on the bus for one system clock period before driving MRDC# active. Both signals are active
low.

SMWTC# (O), MWTC# (I/O)

These signals instruct the memory devices to store the data present on the data bus. SMWTC#
is active only when the memory decode is within the low 1MB of the memory space. MWTC#
is active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA
controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB
of memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have
the address lines valid on the bus for one system clock period before driving MWTC# active.
Both signals are active low.

T-C (O)

Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached.

Manual Number: 40110-005-2 Page 23

I/O Address Map

Hex Range Device

000-01F DMA Controller 1
020-03F Interrupt Controller 1, Master
040-05F Timer
060-06F 8042 (keyboard)
070-07F Realtime Clock, NMI (non-maskable interrupt) Mask
080-09F DMA Page Register

0A0-0BF Interrupt Controller 2

0C0-ODF DMA Controller 2

0F0 Clear Math Coprocessor Busy

0F1 Reset Math Coprocessor
0F8-0FF Math Coprocessor
1F0-1F8 Fixed Disk
200-207 Game I/O
278-27F Parallel Printer Port 2
2F8-2FF Serial Port 2
300-31F Prototype Card
360-36F Reserved
378-37F Parallel Printer Port 1
380-38F SDLC, Bisynchronous 2

3A0-3AF Bisynchronous 1
3B0-3BF Monochrome Display and Printer Adapter
3C0-3CF Reserved
3D0-3DF Color/Graphics Monitor Adapter

3F0-3F7 Diskette Controller
3F8-3FF Serial Port 1

Manual Number: 40110-005-2Page 24

Interrupt Assignments *

Interrupt Description

IRQ0 Timer Output 0
IRQ1 Keyboard (Output Buffer Full)
IRQ2 Interrupt 8 through 15
IRQ3 Se rial Por t 2
IRQ4 Se rial Por t 1
IRQ5 Pa ralle l Port 2
IRQ6 Diskette Controller
IRQ7 Pa ralle l Port 1
IRQ8 Realtime Clock Interrupt

IRQ9 Software R edirec ted to INT 0AH (IR Q2)
IR Q1 0 Una ssi g ned
IR Q11 U na s s i gne d
IRQ12 PS/2 Mouse
IRQ13 Coprocessor
IRQ14 Fixed Disk Controller

IRQ15

Unassigned (may be assigned by the system to the

system to the secondary IDE)

* These are typical parameters, which may not reflect your current system.

Manual Number: 40110-005-2 Page 25

PCI Local Bus

PCI Overview

The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or 64-bit
bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism
between highly integrated peripheral controller components, peripheral add-in boards and proces­sor/memory systems.

The “local bus” moves peripheral functions with high bandwidth requirements closer to the system’ s
processor bus and can produce substantial performance gains with graphical user interfaces (GUI’s)
and other high bandwidth functions (i.e., full motion video, SCSI, LAN’s, etc.). The PCI Local
Bus accommodates future system requirements and is applicable across multiple platforms and
architectures.

The PCI component and add-in card interface is processor independent, enabling an efficient tran­sition to future processor generations, by bridges or by direct integration, and use with multiple
processor architectures.

Processor independence allows the PCI Local Bus to be optimized for I/O functions, enables con­current operation of the local bus with the processor/memory subsystem, and accommodates mul­tiple high performance peripherals in addition to graphics. Movement to enhanced video and
multimedia displays and other high bandwidth I/O will continue to increase local bus bandwidth
requirements. A transparent 64-bit extension of the 32-bit data and address buses is defined, dou­bling the bus bandwidth and offering forward and backward compatibility of 32-bit (132MB/s
peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals.

PCI Local Bus Signal Definition

The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for a master
to handle data and addressing, interface control, arbitration and system functions. The diagram
below shows the pins in functional groups, with required pins on the left side and optional pins on
the right side.

Manual Number: 40110-005-2Page 26

PCI Local Bus Pin Numbering

Manual Number: 40110-005-2 Page 27

PCI Local Bus Pin Assignments

The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The bus pin assign­ments shown below are for the 5-volt connector. The 3.3-volt connector bus pin assignments are
the same with the following exceptions:

* The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which connector is being

used.

† Pins B12, B13, A12 and A13 are Gnd (ground) on the 5-volt connector, but are Connector Keys

on the 3.3-volt connector.

†† Pins B50, B51, A50 and A51 are Connectors Keys on the 5-volt connector, but are Gnd (ground)

on the 3.3-volt connector.

I/O Pin Signal Name

B1 -12 V
B2 T CK
B3 Gn d
B4 TDO
B5 + 5V
B6 + 5V
B7 INT B#
B8 I NT D#

B9 PRSNT1#
B10 Reserved
B11 PRS NT 1#
B12 Gnd †
B13 Gnd †
B14 Reserved
B15 Gnd
B16 CLK
B17 Gnd
B18 REQ#
B19 + V (I/O )
B20 AD 31
B21 AD 29
B22 Gn d

I/O Pin Signal Name

A1 TRST#
A2 +12V
A3 TMS
A4 TDI
A5 +5V
A6 INTA#
A7 INTC#
A8 +5V

A9 Reserved
A10 +V (I/O)
A11 Reserved
A12 Gnd †
A13 Gnd †
A14 Reserved
A15 RST#
A16 +V (I/O)
A17 GNT#
A18 Gnd
A19 Reserved
A20 AD30
A21 +3.3V
A22 AD28

Manual Number: 40110-005-2Page 28

PCI Local Bus Pin Assignments (continued)

I/O Pin Si gn al Na me

B23 AD27
B24 AD25
B2 5 +3. 3V
B26 C/BE3#
B27 AD23
B28 Gnd
B29 AD21
B30 AD19
B3 1 +3. 3V
B32 AD17
B33 C/BE2#
B34 Gnd
B35 IRDY#
B3 6 +3. 3V
B37 DEVSE L#
B38 Gnd
B39 LOCK#
B40 PERR#
B4 1 +3. 3V
B42 SERR#
B4 3 +3. 3V
B44 C/BE1#
B45 AD14
B46 Gnd
B47 AD12
B48 AD10
B49 Gnd
B50 Connector key ††
B51 Connector key ††
B52 AD8
B53 AD7
B5 4 +3. 3V
B55 AD5
B56 AD3
B57 Gnd
B58 AD1
B59 +V (I/O)
B60 ACK64#
B61 +5V
B62 +5V

I/O Pin Si gn al Na me

A23 AD26
A24 Gnd
A25 AD24
A26 IDSEL
A27 + 3.3V
A28 AD22
A29 AD20
A30 Gnd
A31 AD18
A32 AD16
A33 + 3.3V
A34 FRAME#
A35 Gnd
A36 TRDY#
A37 Gnd
A38 STOP#
A39 + 3.3V
A40 SDONE
A41 SBO#
A42 Gnd
A43 PAR
A44 AD15
B4 5 +3. 3V
B46 AD13
B47 AD11
B48 Gnd
B49 AD9
B50 Connector key ††
B51 Connector key ††
B52 C/BE0#
B5 3 +3. 3V
B54 AD6
B55 AD4
B56 Gnd
B57 AD2
B58 AD0
B59 +V (I/O)
B60 REQ64#
B61 +5V
B62 +5V

Manual Number: 40110-005-2 Page 29

PCI Local Bus Pin Assignments (continued)

I/O Pin Signal Name

Connector Key
Connector Key

B63 Reserved
B64 Gnd
B65 C/BE6#
B66 C/BE4#
B67 Gnd
B68 AD63
B69 AD61
B70 +V (I/O)
B71 AD59
B72 AD57
B73 Gnd
B74 AD55
B75 AD53
B76 Gnd
B77 AD51
B78 AD49

I/O Pin Signal Name

Connector Key
Connector Key

A63 Gnd
A64 C /BE7 #
A65 C /BE5 #
A66 +V ( I/O)
A67 PAR64
A68 AD 62
A69 Gnd
A70 AD 60
A71 AD 58
A72 Gnd
A73 AD 56
A74 AD 54
A75 +V ( I/O)
A76 AD 52
A77 AD 50

A78 Gnd
B79 +V (I/O)
B80 AD47
B81 AD45
B82 Gnd
B83 AD43
B84 AD41
B85 Gnd
B86 AD39
B87 AD37
B88 +V (I/O)
B89 AD35
B90 AD33
B91 Gnd
B92 Reserved
B93 Reserved
B94 Gnd

A79 AD 48

A80 AD 46

A81 Gnd

A82 AD 44

A83 AD 42

A84 +V ( I/O)

A85 AD 40

A86 AD 38

A87 Gnd

A88 AD 36

A89 AD 34

A90 Gnd

A91 AD 32

A92 Rese rved

A93 Gnd

A94 Rese rved

Manual Number: 40110-005-2Page 30

The PCI Local Bus signals are described below and may be categorized into the following func­tional groups:

• System Pins

• Address and Data Pins

• Interface Control Pins

• Arbitration Pins (Bus Masters Only) Error Reporting Pins

• Interrupt Pins (Optional)

• Cache Support Pins (Optional)

• 64-Bit Bus Extension Pins (Optional)

• JTAG/Boundary Scan Pins (Optional)

A # symbol at the end of a signal name indicates that the active state occurs when the signal is at a
low voltage. When the # symbol is absent, the signal is active at a high voltage.

The following are descriptions of the PCI Local Bus signals.

ACK64# (optional)

Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded
its address as the target of the current access, indicates the target is willing to transfer data using
64bits. ACK64# has the same timing as DEVSEL#.

AD[31::00]

Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address
phase followed by one or more data phases. During the address phase, AD[31::00] contain a
physical address (32 bits). During data phases, AD[07::00] contain the least significant byte
(lsb) and AD[31::24] contain the most significant byte (msb).

AD[63::32] (optional)

Address and Data are multiplexed on the same pins and provide 32<N>additional bits. During
an address phase (when using the DAC command and when REQ64# is asserted), the upper
32bits. of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and
indeterminate. During a data phase, an additional 32bits. of data are transferred when REQ64#
and ACK64# are both asserted.

C/BE[3::0]#

Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase
of a transaction, these pins define the bus command; during the data phase they are used as byte
enables. The byte enables are valid for the entire data phase and determine which byte lanes carry
meaningful data. C/applies to byte(lsb) and applies to byte 3 (msb).

Manual Number: 40110-005-2 Page 31

C/BE[7::4]# (optional)

Bus Command and Byte Enables are multiplexed on the same pins. During an address phase
(when using the DAC command and when REQ64# is asserted), the actual bus command is
transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data
phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when
REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to byte7

CLK

Clock provides timing for all transactions on PCI and is an input to every PCI device.

DEVSEL#

Device Select, when actively driven, indicates that the driving device has decoded its address as
the target of the current access. As an input, DEVSEL# indicates whether any device on the bus
has been selected.

FRAME#

Cycle Frame is an interface control pin which is driven by the current master to indicate the
beginning and duration of an access. When FRAME# is asserted, data transfers continue; when
it is deserted, the transaction is in the final data phase.

GNT#

Grant indicates to the agent that access to the bus has been granted. This is a point to point signal.
Every master has its own GNT#.

IDSEL

Initialization Device Select is used as a chip select during configuration read and write
transactions.

INTA#, INTB#, INTC#, INTD# (optional)

Interrupts on PCI are optional and defined as “level sensitive,” asserted low (negative true), using
open drain output drivers. PCI defines one interrupt for a single function and up to four interrupt
lines for a multifunction device or connector.

Interrupt A is used to request an interrupt. For a single function device, only INTA# may be used,
while the other three interrupt lines have no meaning.

Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have
meaning on a multifunction device.

IRDY#

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data
phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY#
indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is
prepared to accept data.

Manual Number: 40110-005-2Page 32

LOCK#

Lock indicates an operation that may require multiple transactions to complete. When LOCK#
is asserted, nonexclusive transactions may proceed to an address that is not currently locked.

PAR

Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI
agents. The master drives PAR for address and write data phases; the target drives PAR for read
data phases.

PAR64 (optional)

Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#. The
master drives PAR64 for address and write data phases; the target drives PAR64 for read data
phases.

PERR#

Parity Error is for the reporting of data parity errors during all PCI transactions except a Special
Cycle. There are no special conditions when a data parity error may be lost or when reporting
of an error may be delayed.

PRSNT1# and PRSNT2#

PRSNT1# and PRSNT2# are related to the connector only, not to other PCI components. They
are used for two purposes: indicating that a board is physically present in the slot and providing
information about the total power requirements of the board.

REQ#

Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal.
Every master has its own REQ#.

REQ64# (optional)

Request 64-bit Transfer, when actively driven by the current bus master, indicates it desires to
transfer data using 64 bits. REQ64# has the same timing as FRAME#. REQ64# has meaning
at the end of reset.

RST#

Reset is used to bring PCI-specific registers, sequencers and signals to a consistent state.

SBO# (optional)

Snoop Backoff is an optional cache support pin which indicates a hit to a modified line when
asserted. When SBO# is deserted and SDONE is asserted, it indicates a “clean” snoop result.

Manual Number: 40110-005-2 Page 33

SDONE (optional)

Snoop Done is an optional cache support pin which indicates the status of the snoop for the
current access. When deserted, it indicates the result of the snoop is still pending. When asserted,
it indicates the snoop is complete.

SERR#

System Error is for reporting address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be catastrophic. If an agent does not
want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is
required.

STOP#

Stop indicates that the current target is requesting the master to stop the current transaction.

TCK (optional)

Test Clock is used to clock state information and test data into and out of the device during
operation of the TAP (Test Access Port).

TDI (optional)

Test Data Input is used to serially shift test data and test instructions into the device during TAP
(Test Access Port) operation.

TDO (optional)

Test Data Output is used to serially shift test data and test instructions out of the device during
TAP (Test Access Port) operation.

TMS (optional)

Test Mode Select is used to control the state of the TAP (Test Access Port) controller in the
device.

TRDY#

Target Ready indicates the target agent’s (selected device’s) ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. During a read, TRDY#
indicates that valid data is present on AD[31::00]. During a write, it indicates that the target is
prepared to accept data.

TRST# (optional)

Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional
in the IEEE Standard Test Access Port and Boundary Scan Architecture.

Manual Number: 40110-005-2Page 34

Chapter 3: BIOS Operation

Sections 3 through 7 of this manual describe the operation of the American Megatrends Hi-Flex
AMIBIOS and the AMIBIOS Setup Utility . Refer to Running AMIBIOS Setup later in this section
for standard Setup screens, options and defaults.

When the system is powered on, AMIBIOS performs the Power-On Self Test (POST) routines.
These routines are divided into two phases:

1. System Test and Initialization. Test and initialize system boards for normal operations.

2. System Configuration Verification. Compare defined configuration with hardware actually
installed.

If an error is encountered during the diagnostic tests, the error is reported in one of two different
ways. If the error occurs before the display device is initialized, a series of beeps is transmitted. If
the error occurs after the display device is initialized, the error message is displayed on the screen.
See BIOS Errors later in this section for more information on error handling.

The following are some of the Power-On Self Tests (POST’s) which are performed when the sys­tem is powered on:

• CMOS Checksum Calculation

• Keyboard Controller Test

• CMOS Shutdown Register Test

• 8254 Timer Test

• Memory Refresh Test

• Display Memory Read/Write Test

• Display Type Verification

• Entering Protected Mode

• Memory Size Calculation

• Conventional and Extended Memory Test DMA Controller Tests

• Keyboard Test

• System Configuration Verification and Setup

Note: When you perform a warm boot by pressing <Ctrl><Alt><Del>all memory tests are by-

passed.

AMIBIOS checks all system and cache memory and reports them on both the initial AMIBIOS
screen and the AMIBIOS System Configuration screen which appears after POST is completed.
AMIBIOS attempts to initialize the peripheral devices by verifying the validity of the system setup
information stored in the system CMOS RAM. (See the Running AMIBIOS Setup section of this
manual.) If AMIBIOS detects a fault, the screen displays the error condition(s) which has/have
been detected. If no errors are detected, AMIBIOS attempts to load the system from any bootable
device, such as a floppy disk or hard disk.

Manual Number: 40110-005-2 Page 35

Normally, the only POST routine visible on the screen is the memory test. The following screen
displays when the system is powered on:

AMIBIOS (C)1996 American Megatrends Inc.
INDUSTRIAL COMPUTER SOURCE
Hit DEL if you want to run SETUP

Initial Power-On Screen

You have two options:

• Press <Del> to access the AMIBIOS Setup Utility.
This option allows you to change various system parameters such as date and time, disk drives,

etc. The Running AMIBIOS Setup section of this manual describes the options available.
Y ou may be requested to enter a password before gaining access to the AMIBIOS Setup Utility .

(See Password Entry later in this section.)
If you enter the correct password or no password is required, the AMIBIOS Setup Main Menu

displays. (See Running AMIBIOS Setup later in this section.)

• Allow the bootup process to continue without invoking the AMIBIOS Setup Utility.
In this case, after AMIBIOS loads the system, you may be requested to enter a password. (See

Password Entry later in this section.)

Once the POST routines complete successfully, a screen displays showing the current configura­tion of your system, including processor type, base and extended memory amounts, floppy and
hard drive types, display type and peripheral ports.

In systems with more than 1MB, AMIBIOS reports 384KB less RAM than it finds, because it
accounts for the address space between 640K and 1024K which is unavailable to DOS. This space
is used for video RAM, video BIOS, system BIOS and adapter ROMs.

Password Entry

The system may be configured so that the user is required to enter a password each time the system
boots or whenever an attempt is made to enter AMIBIOS Setup. The password function may also
be disabled so that the password prompt does not appear under any circumstances.

The Password Check option in the Advanced CMOS Setup program allows you to specify when
the password prompt displays: Always or only when Setup is attempted. The supervisor and user
passwords may be changed using the Change Supervisor Password and Change User Password
options on the AMIBIOS Setup Main Menu. If the passwords are null, the password prompt does
not display at any time. A more detailed description of the password setup function may be found
in the Running AMIBIOS Setup section of this manual.

When password checking is enabled, the following password prompt displays:

Enter CURRENT Password:

Type the password and press <Enter> .

Manual Number: 40110-005-2Page 36

Note : The null password is the system default and is in effect if a password has not been assigned

or if the CMOS has been corrupted. In this case, the password prompt does not display . To
set up passwords, you may use the Change Supervisor Password and Change User Pass­word options on the AMIBIOS Setup Main Menu. (See the Running AMIBIOS Setup
section of this manual.)

If an incorrect password is entered, the following screen displays:

Enter CURRENT Password: X
Enter CURRENT Password:

Y ou may try again to enter the correct password. If you enter the password incorrectly three times,
the system responds in one of two different ways, depending on the value specified in the Pass­word Check option on the Advanced CMOS Setup screen:

1. If the Password Check option is set to Setup , the system does not let you enter Setup, but does
continue the booting process. You must reboot the system manually to retry entering the
password.

2. If the Password Check option is set to Always , the system locks and you must reboot. After
rebooting, you will be requested to enter the password.

Once the password has been entered correctly, you are allowed to continue.

BIOS Errors

If an error is encountered during the diagnostic checks performed when the system is powered on,
the error is reported in one of two different ways:

1. If the error occurs before the display device is initialized, a series of beeps is transmitted.

2. If the error occurs after the display device is initialized, the screen displays the error message.
In the case of a nonfatal error, a prompt to press the <F1> key may also appear on the screen.

Explanations of the beep codes and BIOS error messages may be found in Appendix A - BIOS
Messages .

As the POST routines are performed, test codes are presented on Port80H. These codes may be
helpful as a diagnostic tool and are listed in Appendix A - BIOS Messages .

If certain nonfatal error conditions occur, you are requested to run the AMIBIOS Setup Utility.
The error messages are followed by this screen:

AMIBIOS (C)1996 American Megatrends Inc.
INDUSTRIAL COMPUTER SOURCE
RUN SETUP UTILITY
Press F1 to Resume

Press <F1> . You may be requested to enter a password before gaining access to the AMIBIOS
Setup Utility. (See Password Entry earlier in this section.)

Manual Number: 40110-005-2 Page 37

If you enter the correct password or no password is required, the AMIBIOS Setup Main Menu
displays.

Running AMBIOS Setup

AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives, display
type and other user-defined parameters. The Setup parameters reside in the Read Only Memory
Basic Input/Output System (ROM BIOS) so that they are available each time the system is turned
on. AMIBIOS Setup stores the information in the complementary metal oxide semiconductor
(CMOS) memory. When the system is turned off, a backup battery retains system parameters in the
CMOS memory.

Each time the system is powered on, it is configured with these values, unless the CMOS has been
corrupted or is faulty. The AMIBIOS Setup Utility is resident in the ROM BIOS (Read Only
Memory Basic Input/Output System) so that it is available each time the computer is turned on. If,
for some reason, the CMOS becomes corrupted, the system is configured with the default values
stored in this ROM file.

As soon as the system is turned on, the power-on diagnostic routines check memory, attempt to
prepare peripheral devices for action, and offer you the option of pressing <Del> to run AMIBIOS
Setup.

If certain nonfatal errors occur during the Power-On Self T est (POST) routines which are run when
the system is turned on, you may be prompted to run AMIBIOS Setup by pressing <F1>.

System BIOS Setup Utilities

The System BIOS is an American Megatrends Hi-Flex AMIBIOS with ROM-resident setup utili­ties. The following Setup utilities are selectable from the AMIBIOS Hi-Flex Setup Utility Menu:

• Standard CMOS Setup

• Advanced CMOS Setup

• Advanced Chipset Setup

• PCI/Plug and Play Setup

• Peripheral Setup

• Auto-Detect Hard Disks

• Change User Password

• Change Supervisor Password

• Auto Configuration with Optimal Settings

• Auto Configuration with Fail Safe Settings

• Save Settings and Exit

• Exit Without Saving

Manual Number: 40110-005-2Page 38

AMIBIOS Setup Main Menu

When you press <F1> in response to an error message received during the POST routines or when
you press the <Del> key to enter the AMIBIOS Setup Program, the following screen displays:

AMIBIOS Setup Main Menu

Use the Down Arrow key to highlight the desired option and press <Enter> .

• Select Standard CMOS Setup to make changes to Standard CMOS Setup parameters.

The Setup program is described in the Standard CMOS Setup section of this manual. The
following options may be changed:

• Date/Time

• Floppy Drive A:/Floppy Drive B: Types

• Primary Master and Slave Disk Types

• Secondary Master and Slave Disk Types

• Logical Block Address (LBA) Mode

• Block Mode

• PIO Mode

• 32Bit Mode

• Boot Sector Virus Protection

• Select Advanced CMOS Setup to make changes to Advanced CMOS Setup parameters.

The Setup program is described in the Advanced Setup section of this manual. The
following options may be changed:

• Quick Boot

• BootUp Sequence

• BootUp Num-Lock

• Floppy Drive Swap

• Floppy Drive

• Mouse Support

• System Keyboard

• Primary Display

• Password Check

• Parity Check

• OS/2 Compatible Mode

• Wait For ‘F1’ If Error

• Hit ‘DEL’ Message Display

• Internal Cache

• System BIOS

• Video and Adapter ROM Shadow

Manual Number: 40110-005-2 Page 39

• Select Advanced Chipset Setup to make changes to Advanced Chipset Setup parameters.
The Setup program is described in the Advanced Setup section of this manual. The
following options may be changed:

• DRAM Speed

• DRAM Integrity Mode (ECC) DRAM Fast Leadoff

• DRAM Refresh Queue

• VGA Frame Buffer USWC

• PCI Frame Buffer USWC

• Fixed Memory Hole

• CPU to IDE Posting

• USWC Write Posting

• CPU to PCI Posting

• PCI to DRAM Pipeline

• PCI Burst Write Combine

• Read Around Write

• TypeF DMA Buffer Controls 1 and 2 USB Function Enable

• USB Keyboard Support

• USB Passive Release Enable

• Select PCI/Plug and Play Setup to make changes to PCI/Plug and Play Setup parameters.
The Setup program is described in the PCI/Plug and Play Setup section of this manual.
The following options may be changed:

• Plug and Play Aware O/S

• PCI Latency Timer

• PCI VGA Palette Snoop

• PCI IDE BusMaster

• OffBoard PCI IDE Card

• OffBoard PCI IDE Primary and Secondary IRQs

• DMA Channels 0, 1, 3, 5, 6 and 7

• IRQ5 /IRQ9/IRQ10/IRQ11/

• Reserved Memory Size and Address

• On Board SCSI

• On Board VGA

• Select Peripheral Setup to make changes to the Peripheral Setup parameters. The Setup
program is described in the Peripheral Setup section of this manual. The following op
tions may be changed:

• OnBoard FDC

• OnBoard Serial Ports 1 and 2

• OnBoard Parallel Port

• Parallel Port Mode

Manual Number: 40110-005-2Page 40

• OnBoard IDE

• Select Auto-Detect Hard Disks to have AMIBIOS automatically detect the type and pa

rameters of each hard drive if you have IDE drive(s). This option is described later in this
section.

• Select Change User Password to establish or change the password for the user. This

function is described later in this section.

• Select Change Supervisor Password to establish or change the password for the supervi

sor. This function is described later in this section.

• Select Auto Configuration with Optimal Settings to load the Optimal default settings.

These settings are best-case values which should provide the best performance characteris
tics. This function is described later in this section.

• Select Auto Configuration with Fail Safe Settings to load the Fail Safe default settings.

These settings are more likely to configure a workable computer, but they may not provide
optimal performance. This function is described later in this section.

• Select Save Settings and Exit to store your changes in the CMOS. The CMOS checksum

is calculated and written to the CMOS. Control is then passed back to AMIBIOS and the
booting process continues, using the new CMOS values. This function is described later in
this section.

• Select Exit Without Saving to pass control back to the AMIBIOS without writing any

changes to the CMOS. AMIBIOS continues with the booting process. This function is
described later in this section.

Auto-Detect Hard Disks

The Auto-Detect Hard Disks option allows you to have AMIBIOS automatically detect the type of
hard disk drive(s) in your system. The automatic detection functions only if you have IDE drives.
The parameters are reported on the Standard CMOS Setup screen.

AMIBIOS searches first for the primary master and slave hard disk drives, then for the secondary
master and slave drives. If it can access a drive, it reads the disk parameters. It then searches the
AMIBIOS drive type table for matching parameters to determine the disk type and displays both
the type and parameters on the screen. If no matching parameters are found in the table, AMIBIOS
specifies the type as “User” and fills in the parameter values it found on the drive. If it cannot
access the drive or if it is not an IDE drive, AMIBIOS times out and specifies that the disk drive is
“Not Installed.”

Note : The auto detect feature displays disk parameter values as established by the drive manufac-

turer. If the drive has been formatted using any other values, accepting the auto detect
values will cause erratic behavior. You must either reformat the drive to meet the
manufacturer’s specifications or use Standard CMOS Setup to enter parameters which
match the current format of the drive.

Manual Number: 40110-005-2 Page 41

If you do not want to accept the hard disk type and its associated parameters as reported by AMIBIOS
or if the drive is “Not Installed,” you may use Standard CMOS Setup to set up the correct param­eters for the drive.

Once the parameters are correct for all of the drives, you may exit from the Standard CMOS Setup
screen and save the settings in the CMOS.

Change Password

AMIBIOS Setup has an optional password feature which can be configured so that a password
must be entered each time the system boots or just when a user attempts to enter AMIBIOS Setup.
(See the Advanced CMOS Setup section of this manual for information on how to enable the
Password Check option.)

The Change Supervisor Password and Change User Password options on the AMIBIOS Setup
Main Menu allow you to establish passwords, change the current passwords or disable the pass­word prompts by entering null passwords. The passwords are stored in CMOS RAM. The Change
User Password function is accessible only if the supervisor password has been established previ­ously. If you have signed on under the user password, you cannot change the supervisor password.

Note : The null password is the system default and is in ef fect if a password has not been assigned

or if the CMOS has been corrupted. In this case, the “Enter CURRENT Password” prompt
is bypassed when you boot the system, and you must establish a new password.

Change Supervisor Password

If you select the Change Supervisor Password option, the following window displays:

Enter new supervisor password: _

This is the message which displays before you have established a password, or if the last password
entered was the null password. If a password has already been established, you are asked to enter
the current password before being prompted to enter the new password.

Type the new password and press <Enter> . The password cannot exceed six (6) characters in
length. The screen does not display the characters as you type them.

After you have entered the new password, the following window displays:

Enter new supervisor password: _

Re-key the new password as described above.

If the password confirmation is mis-keyed, AMIBIOS Setup displays the following message:

Incorrect password, press any key to continue

No retries are permitted; you must restart the procedure from the AMIBIOS Setup Main Menu.

Manual Number: 40110-005-2Page 42

If the password confirmation is entered correctly, the following message displays:

New supervisor password installed, press any key to continue

When you press any key, the screen returns to the AMIBIOS Setup Main Menu screen, which
allows you to save the password change or exit from Setup without saving the new password. To
save the new password in CMOS memory, be sure to select Save Settings and Exit .

If you save the changes when you exit AMIBIOS Setup, the password is stored in CMOS RAM.
The next time the system boots, you are prompted for the password if the password function is
present and is enabled. (See Advanced CMOS Setup later in this manual for an explanation of
how to enable password checking.)

Note : Be sure to keep a record of the new password each time it is changed. If you forget it, use

the Password Clear jumper to reset it to the default (null password). See the Specifica­tions section of this manual for details.

Change User Password

The Change User Password function is accessible only if the supervisor password has been estab­lished previously.

The Change User Password option is similar in functionality to the Change Supervisor Password
and displays the same messages, except that “user” replaces “supervisor.” If you have signed on
under the user password, you cannot change the supervisor password.

Disabling the Password(s)

To disable password checking so that the password prompt does not appear under any circum­stances, you may create null passwords using the Change Supervisor Password and Change User
Password functions by pressing <Enter> without typing in a new password. You will be asked to
confirm the password. Select <Enter> again and the following message displays:

When you press any key, the screen returns to the AMIBIOS Setup Main Menu, which allows you
to save the password change or exit from Setup without saving the null password. To save the null
password(s) in CMOS memory, be sure to select Save Settings and Exit .

Auto Configuration Options

Each AMIBIOS Setup option has two default settings (Optimal and Fail Safe). These settings can
be applied to all AMIBIOS Setup options when you select the appropriate auto configuration op­tion from the AMIBIOS Setup Main Menu.

You can use these auto configuration options to quickly set the system configuration parameters
which should provide the best performance characteristics, or you can select a group of settings
which have a better chance of working when the system is having configuration-related problems.

Manual Number: 40110-005-2 Page 43

Auto Configuration with Optimal Settings

This option allows you to load the Optimal default settings. These settings are best-case values
which should provide the best performance characteristics. If CMOS RAM is corrupted, the Opti­mal settings are loaded automatically.

If you select the Auto Configuration with Optimal Settings option, the following window displays:

Load high performance settings (Y/N) ? N

You have two options:

• Press ‘ N ‘ and <Enter> to leave the current values in effect.

• Press ‘ Y ‘ and <Enter> to load the Optimal default settings.

Auto Configuration with Fail Safe Settings

This option allows you to load the Fail Safe default settings when you cannot boot your computer
successfully. These settings are more likely to configure a workable computer. They may not
provide optimal performance, but are the most stable settings. You may use this option as a diag­nostic aid if your system is behaving erratically. Select the Fail Safe settings and then try to
diagnose the problem after the computer boots.

If you select the Auto Configuration with Fail Safe Settings option, the following window dis­plays:

Load fail-safe settings (Y/N) ? N

You have two options:

• Press ‘ N ‘ and <Enter> to leave the current values in effect.

• Press ‘ Y ‘ and <Enter> to load the Fail Safe default settings.

Save Settings and Exit

The features selected and configured in the Setup screens are stored in the CMOS when this option
is selected. The CMOS checksum is calculated and written to the CMOS. Control is then passed
back to the AMIBIOS and the booting process continues, using the new CMOS values.

If you select the SAVE SETTINGS AND EXIT option, the following window displays:

Save current settings and exit (Y/N) ? Y

You have two options:

• Press ‘ N ‘ and <Enter> to return to the AMIBIOS Setup Main Menu.

• Press ‘ Y ‘ and <Enter> to save the system parameters and continue with the booting
process.

Manual Number: 40110-005-2Page 44

Exit Without Saving

This option passes control back to AMIBIOS without writing any changes to the CMOS.

If you select the EXIT WITHOUT SAVING option, the following window displays:

Quit without saving the current settings (Y/N) ? N

You have two options:

• Press ‘ N ‘ and <Enter> to return to the AMIBIOS Setup Main Menu.

• Press ‘ Y ‘ and <Enter> to continue with the booting process without saving any system
parameters.

Key Conventions

Listed below is an explanation of the keys you may use for navigation and selection in the AMIBIOS
Setup Utility:

Key Task

<ESC>

<TAB> Move to the next field.

Arrow Keys Move to the next field in the desired direction.

<ENTER> Select the current item.

<F2>/<F3> Change background and foreground colors.

<F10>

Plus Key (+), <PgUp> Increment a value.

Minus Key (-), <PgDn> Decrement a value.

Close the current operation and return to the

previous level.

Save all changes made to Setup and exit from

the AMBIOS Setup Utility.

Manual Number: 40110-005-2 Page 45

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Manual Number: 40110-005-2Page 46

Chapter 4: Standard CMOS Setup

When you select Standard CMOS Setup from the AMIBIOS Setup Main Menu, the following
Setup screen displays:

AMIBIOS SETUP - STANDARD CMOS SETUP

(C)1996 American Megatrends, Inc. All Rights Reserved

Date (mm/dd/yyyy): Mon Jan 01,1980
Time (hh/mm/ss): 12:30:00

Floppy Drive A: 1.44 MB 3 1/2
Floppy Drive B: Not Installed

LBA Blk PIO 32Bit

Type Size Cyln Head WpcomSec Mode Mode Mode Mode

Pri Master : Auto On On Auto O ff
Pri Slave : Auto On On Auto Off
Sec Master : Auto On On Auto O ff
Sec Slave : Auto On On Auto Off

Boot Sector Virus Protection Disabled
Month: Jan - Dec ESC: Exit ↓

Day: 01 - 31 PgUp/PgDn: Modify
Year: 1901 - 2099 F2/F3: Color

The Standard CMOS Setup Screen

When you display the Standard CMOS Setup screen, the format is similar to the sample shown
above. If values display for all parameters, the Setup parameters have been defined previously.
The available values for each option are displayed at the bottom of the screen when you tab or
arrow into the field.

Note: The values on this screen do not necessarily reflect the values appropriate for your processor

board. Refer to the explanations below for specific instructions about entering correct
information.

↑:Sel

Manual Number: 40110-005-2 Page 47

Standard CMOS Options

The descriptions for the system options listed below show the values as they appear if you have not
run the Standard CMOS Setup program yet. Once values have been defined, they display each time
Standard CMOS Setup is run.

Date

The Setup screen displays the system option:

Date (mm/dd/yyyy): Mon Jan 01, 1980

The Help window displays allowable settings:

Month: Jan - Dec
Day: 01 - 31
Year: 1901 - 2099

There are three fields for entering the date. Use the left and right arrow keys or the tab key to move
from one field to another; use the plus and minus (or PgUp and PgDn) keys to scroll through the
allowable values for the field. As you scroll through the month, day or year field, the day of the
week changes automatically to reflect the new date.

Time

The Setup screen displays the system option:

Time (hh/mm/ss): 00:00:00

The Help window displays:

Time is 24 hour format:­Hour:00-23 Minute:00-59 Second:00-59
(1:30AM = 01:30:00, 1:30PM = 13:30:00)

There are three fields for entering the time. Use the left and right arrow keys or the tab key to move
from one field to another; use the plus and minus (or PgUp and PgDn) keys to scroll through the
allowable values for the field.

Floppy Drive A:/Floppy Drive B:

The floppy drive type(s) in your system can be configured using these options.

The Setup screen displays the system options:

Floppy Drive A: 1.44 MB 3-1/2
Floppy Drive B: Not Installed

Manual Number: 40110-005-2Page 48

Available options are:

Not Installed
360 KB 5-1/4

1.2 MB 5-1/4

720 KB 3-1/2

1.44 MB 3-1/2

2.88 MB 3-1/2

The Not Installed option can be used for diskless work stations.

Primary and Secondary Hard Disk Drives

The processor board supports up to four hard disk drives through a primary and secondary control­ler in a master/slave configuration. The primary controller uses I/O port addresses 1F0H through
1F7H, 3F6H and IRQ14. The secondary controller uses I/O port addresses 170H through 177H,
376H and IRQ15.

The AMIBIOS enhanced IDE (EIDE) interface can support IDE Type4 disk drives. This EIDE
interface allows disk drives greater than 528MB to be used.

The hard disk drives can be detected automatically by AMIBIOS (if they are IDE drives) or can be
defined manually by the user, as described below.

The Setup screen displays the system options:

Pri Master: Auto
Pri Slave: Auto
Sec Master: Auto
Sec Slave: Auto

The Help window displays:

1-46: Predefined types
USER: Enter parameters manually
AUTO: Set parameters automatically on each boot
CD-ROM: Use for ATAPI CD-ROM drives Or press ENTER to set all DD parameters

automatically

To set up the hard disk drive parameter(s), use the plus (+) key or PgDn key to scroll through the
drive types to locate the correct type of disk drive(s) in your computer.

Manual Number: 40110-005-2 Page 49

As you scroll through the disk types, the drive Type displays, along with values for size, cylinders,
heads, write precompensation and sectors. Available predefined hard disk drive types are listed at
the end of this section. If the parameters supplied by the manufacturer of your disk drive do not
match any of these preprogrammed drive types, you may have AMIBIOS detect the drive type
automatically (if it is an IDE drive), or you may select the User drive type to enter the parameters
manually as described below.

Set the drive type to CD-ROM to boot from a CD-ROM drive.

Not Installed is available for use as an option. This option can be used for diskless work stations.

Automatic Detection of Drive Type

If any of the hard disks are IDE drives, AMIBIOS can automatically configure the drive type by
detecting the IDE drive parameters and reporting them on the Standard CMOS Setup screen.

You may invoke automatic detection of IDE drives in one of three ways:

• Press Enter when the cursor is in the Type field. AMIBIOS detects the drive type and parameters
as requested. If the drive type is not defined in the drive type table, this option displays User
as the drive type and displays the parameters which were detected by AMIBIOS. The detected
drive type values may then be saved in the CMOS.

• Set the drive type to Auto to have AMIBIOS detect the drive type and parameters automatically
each time the system is booted up. This option does not display the drive type on the Standard
CMOS Setup screen, but does display it on the System Configuration screen shown after a
successful bootup.

• Select the Auto-Detect Hard Disks option on the AMIBIOS Setup Main Menu to have AMIBIOS
automatically detect the type and parameters of each hard drive and place the information into
the Standard CMOS Setup screen. The detected drive type values may then be saved in the
CMOS. This option is described in the Running AMIBIOS Setup section of the System BIOS
chapter of this manual.

Note: The auto detect feature displays disk parameter values as established by the drive manufac-

turer. If the drive has been formatted using any other values, accepting the auto detect
values will cause erratic behavior. You must either reformat the drive to meet the
manufacturer’s specifications or use the User type to enter parameters which match the
current format of the drive.

User-Defined Drive Types

If the parameters supplied by the manufacturer of your disk drive do not match any of the
preprogrammed drive types in the Hard Disk Drive Types table at the end of this section, you may
enter the parameters manually.

The user-defined parameters for each of the four drives may be different, which effectively allows
four different user-definable hard disk types.

Scroll to the end of the drive type list to the User type. You can manually enter the Cyln, Head,
WPcom and Sec parameters. The Size parameter is automatically calculated and displayed by the
system based on the other parameters entered.

Manual Number: 40110-005-2Page 50

Use the arrow keys or tab key to move between fields. Once you have placed the cursor in a field,
type in the correct value.

The following explains the drive parameters which you must enter for a drive type which is not in
the list:

Type is the numeric designation for a drive with certain identification parameters.
Cylinders (Cyln) is the number of disk cylinders found in the specified drive type.
Heads (Head) is the number of disk heads found in the specified drive type.
Write Precompensation (WPcom) is the read delay circuitry which takes into account the

timing differences between the inner and outer edges of the surface of the disk. The size of the
sector gets progressively smaller as the track diameter diminishes. Yet each sector must still hold
512 bytes. Write precompensation circuitry on the hard disk compensates for the physical
difference in sector size by boosting the write current for sectors on inner tracks. This parameter
designates the track (cylinder) number where write precompensation begins.

Sectors (Sec) designates the number of disk sectors per track.
Size is the formatted capacity of the drive (in megabytes) based on the following formula:

# of heads x # of cylinders x # of sects/cyln x 512 bytes/sect

IDE Drive Type Setup Options

For each of the four hard disk drives which is an IDE drive, the following options are also available
for the drive:

Logical Block Addressing (LBA) Mode

This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the specified
primary or secondary IDE drive. Data is accessed by block addresses rather than by the traditional
cylinder-head-sector format. This allows you to use drives larger than 528MB. In LBA mode, the
maximum drive capacity supported is 8.4GB (gigabytes).

If LBA Mode is set to On and is supported by the hard disk drive, and if the drive is formatted,
AMIBIOS enables LBA mode and translates the physical parameters of the drive to logical param­eters. If a hard disk drive which supports LBA mode and has a capacity greater than 528MB was
formatted with LBA mode disabled, AMIBIOS does not enable LBA mode even if the LBA Mode
parameter is set to On in Standard CMOS Setup.

If LBA Mode is set to Off, AMIBIOS uses the physical parameters of the hard disk and does not
translate parameters. The operating system which uses the parameter table then sees only 528MB
of hard disk space even if the drive contains more than 528MB.

Available options are:

Off
On

Manual Number: 40110-005-2 Page 51

Block Mode

This option supports transfer of multiple sectors to and from the specified primary or secondary
IDE drive.

Block mode boosts IDE drive performance by increasing the amount of data transferred during an
interrupt. Block mode allows transfers of up to 64KB per interrupt, whereas only 512 bytes of data
can be transferred per interrupt if block mode is not used.

If Block Mode is set to On and is supported by the IDE drive, AMIBIOS enables multi-sector
transfers. AMIBIOS sets the number of sectors to be transferred per interrupt to the value returned
by the “identify drive” command.

Available options are:

Off
On

Programmed I/O Mode

IDE PIO mode programs timing cycles between the IDE drive and the programmable IDE control­ler. As the PIO mode increases, the cycle time decreases.

Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the IDE drive
being configured. If you select a specific value for the PIO mode, you must make absolutely
certain that you are selecting the PIO mode supported by the IDE drive being configured.

Available options are:

Auto
03
14
25

32Bit Mode

Hard disk drives connected to the processor board via the ISA Bus transfer data 16 bits at a time.
An IDE drive on the PCI Local Bus can use a 32-bit data path.

If the 32Bit Mode parameter is set to On, AMIBIOS enables 32-bit data transfers. If the host
controller does not support 32-bit transfer, this feature must be disabled.

Available options are:

Off
On

Manual Number: 40110-005-2Page 52

Boot Sector Virus Protection

This option allows you to request AMIBIOS to issue a warning when any program or virus issues
a Disk Format command or attempts to write to the boot sector of the hard disk drive.

The Setup screen displays the system option:

Boot Sector Virus Protection Disabled

Available options are:

Disabled
Enabled

If the Boot Sector Virus Protection option is set to Enabled, the following message displays when
a write is attempted to the boot sector.

Boot Sector Write!!! Possible VIRUS: Continue (Y/N)?

Select Y or N as appropriate. You may have to select N several times to prevent the boot sector
write.

The following message displays if any attempt is made to format any cylinder , head or sector of any
hard disk drive via the BIOS INT 13 Hard Disk Drive Service:

Format!!! Possible VIRUS: Continue (Y/N)?

Select Y or N as appropriate. If you select Y to continue, formatting proceeds normally. If you do
not want to continue formatting, you may have to select N several times,

depending on how many retries are performed by the upper-level software. For example, DOS
does at least five retries before the Format utility is actually terminated.

Note: You should not enable boot sector virus protection when formatting a hard drive.

The DOS hard disk Format utility does not use INT13H function AH=05H to format the hard disk.
It only verifies the hard disk using the INT13H Verify function (AH=04H). The virus warning
message is Not displayed during DOS hard disk drive formatting.

Saving and Exiting

When you have made all desired changes to Standard CMOS Setup, press <Esc> to return to the
AMIBIOS Setup Main Menu screen.

Y ou may make changes to other Setup options before exiting from AMIBIOS Setup. You may save
the changes you have just made or you may exit from Setup without saving your changes.

Manual Number: 40110-005-2 Page 53

Using a Worksheet for Setup

Copy this worksheet to record the values needed for the initial CMOS Setup program. Keep a copy
in case of backup battery failure. Consult your drive manual if you are unsure about any of these
values.

Floppy Drive A: Type
Floppy Drive B: Type
Primary Master Disk Type

Cyln* Head* WPcom* Sec* Mode Mode Mode Mode

Primary Slave Disk Type

Cyln* Head* WPcom* Sec* Mode Mode Mode Mode

Secondary Master Disk Type

Cyln* Head* WPcom* Sec* Mode Mode Mode Mode

Secondary Slave Disk Type

Cyln* Head* WPcom* Sec* Mode Mode Mode Mode

LBA Blk PIO 32Bit

LBA Blk PIO 32Bit

LBA Blk PIO 32Bit

LBA Blk PIO 32Bit

* Values required only if Type = User (user-defined type)

Hard Disk Drive Types

Default hard disk drive types defined in the standard BIOS are as follows:

Cyln = Cylinders per drive
Head = Heads per drive
Wpcom = Write precompensation (blank = all; 65535 = none)
Sec = Nbr of sectors per cylinder

Size = Total storage size (Megabytes)

Type Cyln Head Wpcom Sec Size

1 306 4 128 17 10
2 615 4 300 17 20
3 615 6 300 17 30
4 940 8 512 17 62
5 940 6 512 17 46
6 615 4 65535 17 20
7 462 8 256 17 30
8 733 5 65535 17 30
9 900 15 65535 17 112
10 820 3 65535 17 20
11 855 5 65535 17 35

Manual Number: 40110-005-2Page 54

Type Cyln Head Wpcom Sec Size

12 855 7 65535 17 49
13 306 8 128 17 20
14 733 7 65535 17 42
15 Invalid
16 612 4 (blank) 17 20
17 977 5 300 17 40
18 977 7 65535 17 56
19 1024 7 512 17 59
20 733 5 300 17 30
21 733 7 300 17 42
22 733 5 300 17 30
23 306 4 (blank) 17 10
24 925 7 (blank) 17 53
25 925 9 65535 17 69
26 754 7 754 17 43
27 754 11 65535 17 68
28 699 7 256 17 40
29 823 10 65535 17 68
30 918 7 918 17 53
31 1024 11 65535 17 93
32 1024 15 65535 17 127
33 1024 5 1024 17 42
34 612 2 128 17 10
35 1024 9 65535 17 76
36 1024 8 512 17 68
37 615 8 128 17 40
38 987 3 987 17 24
39 987 7 987 17 57
40 820 6 820 17 40
41 977 5 977 17 40
42 981 5 981 17 40
43 830 7 512 17 48
44 830 10 65535 17 68
45 917 15 65535 17 114
46 1224 15 65535 17 152
User
Auto
CDROM
Not Installed

Manual Number: 40110-005-2 Page 55

Chapter 5: Advanced CMOS Setup

When you select Advanced CMOS Setup from the AMIBIOS Setup Main Menu, the following
Setup screen displays:

AMIBIOS SETUP - ADVANCED CMOS SETUP

(C)1996 American Megatrends, Inc. All Rights Reserved
Quick Boot Disabled Available Options:
BootUp Sequence C:,A:,CDROM Disabled
BootUp Num-Lock On Enabled
Floppy Drive Swap Disabled
Floppy Drive Seek Disabled
Mouse Support Enabled
System Keyboard Present
Primary Display VGA/EGA
Password Check Setup
Parity Check Enabled
OS/2 Compatible Mode Disabled
Wait For ‘F1’ If Error Enabled
Hit ‘DEL’ Message Display Enabled
Internal Cache WriteBack
System BIOS Cacheable Enabled
C000,16k, Shadow Cached
C400,16k, Shadow Cached
C800,16k, Shadow Disabled
CC00,16k, Shadow Disabled
D000,16k, Shadow Disabled
D400,16k, Shadow Disabled ESC: Exit ↓↑: Sel
D800,16k, Shadow Disabled PgUp/PgDn: Modify
DC00,16k, Shadow Disabled F2/F3: Color

The Advanced CMOS Setup Screen

When you display the Advanced CMOS Setup screen, the format is similar to the sample shown
above, except the screen displays only twenty options at a time. If you need to change other op­tions, use the down arrow key to locate the appropriate option. The available values for each option
are displayed on the right side of the screen when you tab or arrow into the field. If values display
for all parameters, the Setup parameters have been defined previously.

Note : The values on this screen do not necessarily reflect the values appropriate for your processor

board. Refer to the explanations below for specific instructions about entering correct in­formation.

Manual Number: 40110-005-2Page 56

Advanced CMOS Setup Options

The descriptions for the system options listed below show the values as they appear if you have not
run the Advanced CMOS Setup program yet. Once values have been defined, they display each
time Advanced CMOS Setup is run.

Quick Boot

This option allows you to have the AMIBIOS boot quickly when the computer is powered on or go
through more complete testing.

When this option is set to Disabled , AMIBIOS tests all system memory. It waits up to 40 seconds
for a READY signal from the IDE hard disk drive. It waits for .5 seconds after sending a RESET
signal to the IDE drive to allow the drive time to get ready again. It also checks whether the user has
pressed the <Del> key and runs the AMIBIOS Setup program if the key has been pressed.

If the option is set to Enabled , AMIBIOS checks only the first 1MB of system memory. If a
READY signal is not received immediately from the IDE drive, AMIBIOS does not configure the
drive. It does not wait for .5 seconds after sending a RESET signal to the IDE drive to allow the
IDE drive time to get ready again.

The Setup screen displays the system option:

Quick Boot Disabled

Available options are:

Disabled
Enabled

BootUp Sequence

This option specifies the disk drive sequence the AMIBIOS uses to search for a bootable device
after the AMIBIOS POST routines have completed.

AMIBIOS normally attempts to boot from hard disk C:, if present. If it is unsuccessful, it then
attempts to boot from the floppy drive (either floppy drive A: or floppy drive B:, depending on the
setting of the Floppy Drive Swap option described below). The BootUp Sequence option allows
you to change the bootup sequence to search for the floppy drive and/or the CD-ROM drive before
searching for the C: drive.

The CD-ROM behaves like drive A: if it has a floppy boot image. If it boots as a floppy, it becomes
drive A: and the first floppy drive becomes drive B:. The CD-ROM behaves like a hard drive if it
has a hard disk boot image. If it boots as a hard drive, it becomes drive C: and all other hard disk
drives are shifted one letter (the hard disk drive becomes drive D:).

The Setup screen displays the system option:

BootUp Sequence C:,A:,CDROM

Manual Number: 40110-005-2 Page 57

Available options are:

A:, C:, CDROM
A:,CDROM,C:
C:, A:, CDROM
C:,CDROM,A:
CDROM,A:,C:
CDROM, C:, A:

BootUp Num-Lock

This option enables you to turn off the Num-Lock option on the enhanced keyboard when the
system is powered on. If Num-Lock is turned off, the arrow keys on the numeric keypad can be
used, as well as the other set of arrow keys on the enhanced keyboard.

The Setup screen displays the system option:

BootUp Num-Lock On

Available options are:

Off
On

Floppy Drive Swap

This option allows AMIBIOS to boot from floppy drive B: instead of floppy drive A: when it
searches for a bootable device. The search sequence is defined by the BootUp Sequence option
described above.

The default for this option is Disabled , which causes the system to boot from floppy drive A:.

The Setup screen displays the system option:

Floppy Drive Swap Disabled

Available options are:

Disabled
Enabled

Floppy Drive Seek

This option causes the system to have the floppy drive(s) seek during bootup. The default for this
option is Disabled to allow a fast boot and to decrease the possibility of damage to the heads.

Manual Number: 40110-005-2Page 58

The Setup screen displays the system option:

Floppy Drive Seek Disabled

Available options are:

Disabled
Enabled

Mouse Support

This option indicates whether or not a mouse is supported. If it is set to Enabled , AMIBIOS
supports a PS/2-type mouse.

The Setup screen displays the system option:

Mouse Support Enabled

Available options are:

Disabled
Enabled

System Keyboard

This option indicates whether or not a keyboard is attached to the computer.

The Setup screen displays the system option:

System Keyboard Present

Available options are:

Absent
Present

Primary Display

This option specifies the type of display in the system. The Absent option can be used for network
file servers.

The Setup screen displays the system option:

Primary Display VGA/EGA

Manual Number: 40110-005-2 Page 59

Available options are:

Absent
VGA/EGA
CGA 40 x 25
CGA 80 x 25
Mono (monochrome)

Password Check

This option determines when a password is required for access to the system.

The Setup screen displays the system option:

Password Check Setup

Two options are available:

• Select Setup to have the password prompt appear only when an attempt is made to enter the

AMIBIOS Setup program.

• Select Always to have the password prompt appear each time the system is powered on.

Note : To disable password checking, a null password should be entered in the Change Supervi-

sor Password or Change User Password function in the AMIBIOS Setup Main Menu.

(See the Running AMIBIOS Setup section of this manual.) The null password is the system
default and is in effect if a password has not been assigned or if the CMOS has been
corrupted.

Parity Check

This option allows you to enable parity checking of all system memory.

The Setup screen displays the system option:

Parity Check Enabled

Available options are:

Disabled
Enabled

OS/2 Compatible Mode

This option, when enabled, allows AMIBIOS to run with IBM OS/2 or any other operating system
that does not support Plug and Play.

The Setup screen displays the system option:

OS/2 Compatible Mode Disabled

Manual Number: 40110-005-2Page 60

Available options are:

Disabled
Enabled

Wait For ‘F1’ If Error

Before the system boots up, AMIBIOS executes the Power-On Self Test (POST) routines, a series
of system diagnostic routines. If any of these tests fail but the system can still function, a nonfatal
error has occurred. AMIBIOS responds with an appropriate error message followed by:

Press F1 to Resume

If this option is disabled, a nonfatal error does not generate the “Press F1 to Resume” message.
AMIBIOS still displays the appropriate error message, but continues the booting process without
waiting for the <F1> key to be pressed. This eliminates the need for any user response to a nonfatal
error condition message. Nonfatal error messages are listed in Appendix A - BIOS Messages .

The Setup screen displays the system option:

Wait For ‘F1’ If Error Enabled

Available options are:

Disabled
Enabled

Hit ‘DEL’ Message Display

The ‘Hit DEL if you want to run SETUP’ message displays when the system boots up. Disabling
this option prevents the message from displaying.

The Setup screen displays the system option:

Hit ‘DEL’ Message Display Enabled

Available options are:

Disabled
Enabled

Internal Cache

This option specifies the caching algorithm used for L1 and L2 internal cache memory.

The Setup screen displays the system option:

Internal Cache WriteBack

Manual Number: 40110-005-2 Page 61

Three options are available:

• Select Disabled to disable both L1 internal cache memory on the processor board and L2

secondary cache memory.

• Select WriteBack to use the write-back caching algorithm.

• Select WriteThru to use the write-through caching algorithm.

System BIOS Cacheable

The System BIOS, which is in the F000H memory segment, is automatically shadowed to RAM for
faster execution. This option indicates that this memory segment can be read from or written to L2
secondary cache memory.

The Setup screen displays the system option:

System BIOS Cacheable Enabled

Available options are:

Disabled
Enabled

Video or Adapter ROM Shadow

ROM shadow is a technique in which BIOS code is copied from slower ROM to faster RAM. The
BIOS is then executed from the RAM.

Each option allows for a segment of 16KB to be shadowed from ROM to RAM. If one of these
options is enabled and there is BIOS code present in that particular segment, the BIOS is shad­owed.

Video BIOS shadowing may be done in two 16KB segments at C000H and C400H. Enabling
shadowing can speed up the operation of a machine because RAM can be accessed more rapidly
than ROM and the data bus is wider to RAM. The default setting for the video BIOS segments is
Cached .

Other 16KB ROM segments may be shadowed in the memory area from C800H to E000H, depend­ing upon preferences and system requirements. The ROM area that is not used by ISA adapter
cards is allocated to PCI adapter cards.

The Setup screen displays the system option:

XXXX,16K Shadow Disabled

where XXXX is the base address of the segment of memory to be shadowed.

Manual Number: 40110-005-2Page 62

Three options are available:

• Select Enabled to write the contents of the specified ROM area to the same address in system

memory (RAM) for faster execution.

• Select Cached to write the contents of the specified ROM area to the same address in system

memory (RAM), if an adapter ROM is using the ROM area. This also indicates that the
contents of the RAM area can be read from and written to cache memory.

• Select Disabled if you do not want to copy the specified ROM area to RAM. The contents

of the video ROM cannot be read from or written to cache memory.

Saving and Exiting

When you have made all desired changes to Advanced CMOS Setup , press <Esc> to return to the
AMIBIOS Setup Main Menu screen.

Y ou may make changes to other Setup options before exiting from AMIBIOS Setup. You may save
the changes you have just made or you may exit from Setup without saving your changes.

Advanced Chipset Setup

When you select Advanced Chipset Setup from the AMIBIOS Setup Main Menu, the following
Setup screen displays:

AMIBIOS SETUP - ADVANCED CHIPSET SETUP

(C)1996 American Megatrends, Inc. All Rights Reserved
DRAM Speed (ns) 70 Available Options:
DRAM Integrity Mode (ECC) Disabled 50
DRAM Fast Leadoff Disabled 60
DRAM Refresh Queue Enabled 70
VGA Frame Buffer USWC Disabled
PCI Frame Buffer USWC Disabled
Fixed Memory Hole Disabled
CPU To IDE Posting Enabled
USWC Write Posting Disabled
CPU To PCI Posting Enabled
PCI To DRAM Pipeline Enabled
PCI Burst Write Combine Enabled
Read Around Write Enabled
TypeF DMA Buffer Control1 Disabled
TypeF DMA Buffer Control2 Disabled
USB Function Enable Disabled ESC: Exit ↓↑: Sel
USB Keyboard Support Disabled PgUp/PgDn: Modify
USB Passive Release Enable Enabled F2/F3: Color

The Advanced Chipset Setup Screen

Manual Number: 40110-005-2 Page 63

When you display the Advanced Chipset Setup screen, the format is similar to the sample shown
above. The available values for each option are displayed on the right side of the screen when you
tab or arrow into the field. If values display for all parameters, the Setup parameters have been
defined previously.

Note : The values on this screen do not necessarily reflect the values appropriate for your processor

board. Refer to the explanations below for specific instructions about entering correct in­formation.

Advanced Chipset Setup Options

The descriptions for the system options listed below show the values as they appear if you have not
run the Advanced Chipset Setup program yet. Once values have been defined, they display each
time Advanced Chipset Setup is run.

Note : Do not change the values for the options on this screen unless you understand the impact on

system operation. Depending on your system configuration, selection of other values may
cause unreliable system operation.

DRAM Speed (ns)

This option allows you to select the speed of the DRAMs being used in the processor board. 60 ns
DRAMs provide the best performance.

The Setup screen displays the system option:

DRAM Speed (ns) 70ns

Available options are:

50ns
60ns
70ns

DRAM Integrity Mode (ECC)

This option allows you to enable ECC (Error Checking and Correction) DRAM integrity mode.

The Setup screen displays the system option:

DRAM Integrity Mode (ECC) Disabled

Available options are:

Disabled
Enabled

Note : The Parity Check option on the Advanced Setup screen must be set to Disabled in order

for DRAM error checking to perform correctly.

Manual Number: 40110-005-2Page 64

DRAM Fast Leadoff

The Setup screen displays the system option:

DRAM Fast Leadoff Disabled

Available options are:

Disabled
Enabled

DRAM Refresh Queue

The Setup screen displays the system option:

DRAM Refresh Queue Enabled

Available options are:

Disabled
Enabled

VGA Frame Buffer USWC

The Setup screen displays the system option:

VGA Frame Buffer USWC Disabled

Available options are:

Disabled
Enabled

PCI Frame Buffer USWC

The Setup screen displays the system option:

PCI Frame Buffer USWC Disabled

Available options are:

Disabled
Enabled

Fixed Memory Hole

This option may be used to specify an area in memory which cannot be addressed on the ISA bus.

Manual Number: 40110-005-2 Page 65

The Setup screen displays the system option:

Fixed Memory Hole Disabled

Available options are:

Disabled
512KB-640KB
15MB-16MB

CPU To IDE Posting

This option is used to enable posted messages from the CPU to the IDE controller.

The Setup screen displays the system option:

CPU To IDE Posting Enabled

Available options are:

Disabled
Enabled

USWC Write Posting

When set to Enabled , this option indicates that your system is using USWC memory which is
shared by both video memory and system memory.

The Setup screen displays the system option:

USWC Write Posting Disabled

Available options are:

Disabled
Enabled

CPU To PCI Posting

This option is used to enable posted messages from the CPU to the PCI Bus.

The Setup screen displays the system option:

CPU To PCI Posting Enabled

Available options are:

Disabled
Enabled

Manual Number: 40110-005-2Page 66

PCI To DRAM Pipeline

This option allows you to enable the pipeline from the PCI Bus to system memory.

The Setup screen displays the system option:

PCI To DRAM Pipeline Enabled

Available options are:

Disabled
Enabled

PCI Burst Write Combine

Setting this option to Enabled allows write instructions to be combined in PCI Burst mode.

The Setup screen displays the system option:

PCI Burst Write Combine Enabled

Available options are:

Disabled
Enabled

Read Around Write

When set to Enabled , this option allows read operations to bypass write operations in the memory
controller.

The Setup screen displays the system option:

Read Around Write Enabled

Available options are:

Disabled
Enabled

Type F DMA Buffer Control 1/Type FDMA Buffer Control 2

The Setup screen displays the system options:

Type F DMA Buffer Control 1 Disabled

Type F DMA Buffer Control 2 Disabled

Manual Number: 40110-005-2 Page 67

Available options are:

Channel-0
Channel-1
Channel-2
Channel-3
Disabled
Channel-5
Channel-6
Channel-7

USB Function Enable

This option allows you to set up the Universal Serial Bus (USB).

If this option is set to Disabled , the following two related Universal Serial Bus options are Not
available for modification.

The Setup screen displays the system option:

USB Function Enable Disabled

Available options are:

Disabled
Enabled

USB Keyboard Support

If the USB Function Enable option described above is set to Disabled , this option is Not avail­able for modification.

The Setup screen displays the system option:

USB Keyboard Support Disabled

Available options are:

Disabled
Enabled

USB Passive Release Enable

If the USB Function Enable option described above is set to Disabled , this option is Not avail­able for modification.

Manual Number: 40110-005-2Page 68

The Setup screen displays the system option:

USB Passive Release Enable Enabled

Available options are:

Disabled
Enabled

Saving and Exiting

When you have made all desired changes to Advanced Chipset Setup , press <Esc> to return to
the AMIBIOS Setup Main Menu screen.

Y ou may make changes to other Setup options before exiting from AMIBIOS Setup. You may save
the changes you have just made or you may exit from Setup without saving your changes.

Manual Number: 40110-005-2 Page 69

This page intentionally left blank

Manual Number: 40110-005-2Page 70

Chapter 6: PCI/Plug and Play Setup

When you select PCI/Plug and Play Setup from the AMIBIOS Setup Main Menu, the following
Setup screen displays:

AMIBIOS SETUP - PCI / PLUG AND PLAY SETUP

(C)1996 American Megatrends, Inc. All Rights Reserved
Plug and Play Aware O/S No Available Options:
PCI Latency Timer (PCI Clocks) 64 No
PCI VGA Palette Snoop Disabled Ye s
PCI IDE BusMaster Disabled
OffBoard PCI IDE Card Auto
OffBoard PCI IDE Primary IRQ Disabled
OffBoard PCI IDE Secondary IRQ Disabled
DMA Channel 0 PnP
DMA Channel 1 PnP
DMA Channel 3 PnP
DMA Channel 5 PnP
DMA Channel 6 PnP
DMA Channel 7 PnP
IRQ5 PCI/PnP
IRQ9 PCI/PnP
IRQ10 PCI/PnP
IRQ11 PCI/PnP
IRQ15 PCI/PnP
Reserved Memory Size Disabled
Reserved Memory Address C8000 ESC: Exit↓↑: Sel
On Board SCSI Enabled PgUp/PgDn: Modify
On Board VGA Enabled F2/F3: Color

The PCI / Plug and Play Setup Screen

When you display the PCI / Plug and Play Setup screen, the format is similar to the sample shown
above, except the screen displays only twenty options at a time. If you need to change other
options, use the down arrow key to locate the appropriate option. The available values for each
option are displayed on the right side of the screen when you tab or arrow into the field. If values
display for all parameters, the Setup parameters have been defined previously.

Note: The values on this screen do not necessarily reflect the values appropriate for your proces-

sor board. Refer to the explanations below for specific instructions about entering correct
information.

Manual Number: 40110-005-2 Page 71

PCI/Plug and Play Setup Options

The descriptions for the system options listed below show the values as they appear if you have not
run the PCI/Plug and Play Setup program yet. Once values have been defined, they display each
time PCI/Plug and Play Setup is run.

Plug and Play Aware O/S

This option indicates whether the operating system installed in the computer is Plug and Play­aware. AMIBIOS only detects and enables PnP ISA adapter cards which are required for system
boot. The Windows 95 operating system is PnP-aware and detects and enables all other PnP-aware
adapter cards. Set the option to No if the operating system (such as DOS, OS/2, Windows 3.x) does
not use PnP.

Note: You must set this option correctly or PnP-aware adapter cards installed in your computer

will not be configured properly.

The Setup screen displays the system option:

Plug and Play Aware O/S No

Available options are:

No
Yes

PCI Latency Timer (PCI Clocks)

This option sets the latency of all PCI devices on the PCI Local Bus. The settings are in units equal
to PCI clocks.

The Setup screen displays the system option:

PCI Latency Timer (PCI Clocks) 64

Available options are:

32 160
64 192
96 224
128 248

PCI VGA Palette Snoop

This option indicates whether any ISA adapter card installed in the system requires VGA palette
snooping.

The Setup screen displays the system option:

PCI VGA Palette Snoop Disabled

Manual Number: 40110-005-2Page 72

Available options are:

Disabled
Enabled

PCI IDE BusMaster

This option specifies whether the IDE controller on the PCI Local Bus has bus mastering capabil­ity. AMIBIOS can perform bus master transfers using scatter/gather DMA on the PCI IDE inter­face. No special drivers are needed, but the IDE drive must support PCI bus mastering.

The Setup screen displays the system option:

PCI IDE BusMaster Disabled

Available options are:

Disabled
Enabled

OffBoard PCI IDE Card

This option specifies the PCI expansion slot on the processor board where the off-board PCI IDE
controller is installed, if any. If an off-board PCI IDE controller is used, the on-board IDE control­ler on the processor board is automatically disabled.

If Auto is selected, AMIBIOS automatically determines the correct setting for this option.

This option forces IRQ14 and IRQ15 to PCI slots on the PCI Local Bus. This is necessary to
support non-compliant PCI IDE adapter cards.

If this option is set to Auto, the OffBoard PCI IDE Primary IRQ and OffBoard PCI IDE
Secondary IRQ options may not be modified.

The Setup screen displays the system option:

OffBoard PCI IDE Card Auto

Available options are:

Auto
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6

Manual Number: 40110-005-2 Page 73

OffBoard PCI IDE Primary IRQ/Secondary IRQ

These options specify the PCI interrupts used by the primary and secondary IDE channels on the
off-board PCI IDE controller.

If the OffBoard PCI IDE Card option described above is set to Auto, these options are not avail­able.

The Setup screen displays the system options:

OffBoard PCI IDE Primary IRQ Disabled

OffBoard PCI IDE Secondary IRQ Disabled

Available options are:

Disabled
INTA
INTB
INTC
INTD
Hardwired

DMA Channels 0, 1, 3, 5, 6 and 7

The Setup screen displays the system option:

DMA Channel# PnP

where # is the DMA Channel number.

Available options are:

PnP
ISA/EISA

IRQ5/IRQ9/IRQ10/IRQ11/IRQ15

These options indicate whether or not the specified interrupt request (IRQ) is available for use by
the system for PCI/Plug and Play features or is reserved for use by option cards on the ISA Bus.
This allows you to specify IRQs for use by legacy ISA adapter cards. The IRQ setup options
indicate whether AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS
configurable devices. If more IRQs must be removed from the pool, you can set the IRQ option to
ISA/EISA. On-board I/O is configurable by AMIBIOS; the IRQs used by on-board I/O are config­ured as PCI/PnP.

Manual Number: 40110-005-2Page 74

The Setup screen displays the system option:

IRQ# PCI/PnP

where # is the number of the interrupt request (IRQ) available to the option specified (PCI or
ISA).

Available options:

PCI/PnP
ISA/EISA

Note: If the OnBoard IDE option on the Peripheral Setup screen is set to Secondary or Both,

IRQ15 is assigned by the system and is not available to the user.

Reserved Memory Size

This option specifies the size of the memory area reserved for legacy ISA adapter cards.

If this option is set to Disabled, the Reserved Memory Address option is not available for modifi­cation.

The Setup screen displays the system option:

Reserved Memory Size Disabled

Available options are:

Disabled
16K
32K
64K

Reserved Memory Address

This option specifies the beginning address (in hexadecimal) of the ROM memory area reserved
for use by legacy ISA adapter cards.

If the Reserved Memory Size option is set to Disabled, this option is not available for modifica-
tion.

The Setup screen displays the system option:

Reserved Memory Address C8000

Manual Number: 40110-005-2 Page 75

Available options are:

C0000 D0000
C4000 D4000
C8000 D8000
CC000 DC000

On Board SCSI

This option indicates whether or not the PCI SCSI controller on the processor board is to be used.

The Setup screen displays the system option:

On Board SCSI Enabled

Available options are:

Disabled
Enabled

On Board VGA (Model SB686P

VXXXX Only)

This option allows you to enable or disable the on-board VGA controller and BIOS.

The Setup screen displays the system option:

On Board VGA Enabled

Available options are:

Disabled
Enabled

Saving and Exiting

When you have made all desired changes to PCI/Plug and Play Setup, press <Esc> to return to the
AMIBIOS Setup Main Menu screen.

Y ou may make changes to other Setup options before exiting from AMIBIOS Setup. You may save
the changes you have just made or you may exit from Setup without saving your changes.

Manual Number: 40110-005-2Page 76

Chapter 7: Peripheral Setup

When you select the Peripheral Setup from the AMIBIOS Setup Main Menu, the following Setup
screen displays:

AMIBIOS SETUP - PERIPHERAL SETUP

(C)1996 American Megatrends, Inc. All Rights Reserved
OnBoard FDC Auto Available Options:
OnBoard Serial Port1 Auto Auto
OnBoard Serial Port2 Auto Disabled
OnBoard Parallel Port Auto Enabled
Parallel Port Mode Normal
OnBoard IDE Both

The Peripheral Setup Screen

ESC: Exit ↓↑: Sel
PgUp/PgDn : Modify
F2/F3: Color

When you display the Peripheral Setup screen, the format is similar to the sample shown above.
The available values for each option are displayed on the right side of the screen when you tab or
arrow into the field. If values display for all parameters, the Setup parameters have been defined
previously.

Note : The values on this screen do not necessarily reflect the values appropriate for your proces-

sor board. Refer to the explanations below for specific instructions about entering correct
information.

Peripheral Setup Options

The descriptions for the system options listed below show the values as they appear if you have not
run the Peripheral Setup program yet. Once values have been defined, they display each time
Peripheral Setup is run.

The AMIBIOS allows automatic or manual setup of peripheral devices. The floppy drive control­ler, serial port, parallel port and IDE controller options on the Peripheral Management screen
can each be set to Auto , which causes AMIBIOS to configure the peripherals automatically as
described under each heading below.

When you set these options to values other than Auto , the values you set up manually are used by
AMIBIOS when booting the system. AMIBIOS reports any I/O conflicts after displaying the BIOS
Configuration Summary screen.

Manual Number: 40110-005-2 Page 77

OnBoard FDC

The on-board floppy drive controller may be enabled or disabled using this option.

When this option is set to Auto , AMIBIOS attempts to enable any floppy drive controller on the
ISA Bus. If no floppy controller is found on the ISA Bus, the on-board floppy controller is enabled.

The Setup screen displays the system option:

OnBoard FDC Auto

Available options are:

Auto
Disabled
Enabled

OnBoard Serial Port 1/OnBoard Serial Port 2

Each of these options enables the specified serial port on the processor board and establishes the
base I/O address for the port.

The interrupts used by Serial Port 1 and Serial Port 2 may be assigned by jumper settings.

The Setup screen displays the system options:

OnBoard Serial Port1 Auto

OnBoard Serial Port2 Auto

Available options are:

Auto
Disabled
3F8H
2F8H
3E8H
2E8H

When this option is set to Auto , AMIBIOS also attempts to avoid address conflicts. If the off­board serial ports are configured to specific starting I/O ports via jumper settings, AMIBIOS con­figures the on-board serial ports to avoid conflicts.

AMIBIOS checks the ISA Bus for serial ports. Any off-board serial ports found on the ISA Bus are
left at their assigned addresses. Serial Port 1, the first on-board serial port, is configured with the
first available address and Serial Port 2, the second on-board serial port, is configured with the next

Manual Number: 40110-005-2Page 78

available address. The default address assignment order is 3F8H, 2F8H, 3E8H, 2E8H. Note that
this same assignment order is used by AMIBIOS to place the active serial port addresses in lower
memory (BIOS data area) for configuration as logical COM devices.

After all addresses have been assigned, any remaining on-board serial ports are disabled.

For example, if there is one off-board serial port on the ISA Bus and its address is set to 2F8H,
Serial Port 1 is assigned address 3F8H and Serial Port 2 is assigned address 3E8H. Configuration
is then as follows:

COM1 - Serial Port 1 (at 3F8H)
COM2 - off-board serial port (at 2F8H)
COM3 - Serial Port 2 (at 3E8H)

OnBoard Parallel Port

This option enables the parallel port on the processor board and establishes the base I/O address for
the port. The interrupt used by the Parallel Port may be assigned by a jumper setting.

The Setup screen displays the system option:

OnBoard Parallel Port Auto

Available options are:

Auto
Disabled
378H
278H
3BCH

When this option is set to Auto , AMIBIOS checks the ISA Bus for off-board parallel ports. Any
parallel ports found on the ISA Bus are left at their assigned addresses. The on-board Parallel Port
is automatically configured with the first available address not used by an off-board parallel port.
The default address assignment order is 3BCH, 378H, 278H. Note that this same assignment order
is used by AMIBIOS to place the active parallel port addresses in lower memory (BIOS data area)
for configuration as logical LPT devices.

Parallel Port Mode

This option specifies the parallel port mode. ECP and EPP are both bidirectional data transfer
schemes which adhere to the IEEE P1284 specifications.

The Setup screen displays the system option:

Parallel Port Mode Normal

Manual Number: 40110-005-2 Page 79

Three options are available:

• Normal uses normal parallel port mode.

• EPP allows the parallel port to be used with devices which adhere to the Enhanced Parallel

Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric
bidirectional data transfer driven by the host device.

• ECP allows the parallel port to be used with devices which adhere to the Extended

Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve transfer rates
of approximately 2.5MB/second. ECP provides symmetric bidirectional communication.

OnBoard IDE

This option specifies the on-board integrated drive electronics (IDE) controller channel(s) to be
used.

The Setup screen displays the system option:

OnBoard IDE Both

Available options are:

Both
Disabled
Primary
Secondary

Note : If this option is set to Secondary or Both , the system assigns interrupt request 15 (IRQ15).

Saving and Exiting

When you have made all desired changes to Peripheral Setup , press <Esc> to return to the
AMIBIOS Setup Main Menu screen.

Y ou may make changes to other Setup options before exiting from AMIBIOS Setup. You may save
the changes you have just made or you may exit from Setup without saving your changes.

Manual Number: 40110-005-2Page 80

Appendix A: BIOS Messages

BIOS Beep Codes

Errors may occur during the POST (Power-On Self Test) routines which are performed each time
the system is powered on.

Nonfatal errors are those which, in most cases, allow the system to continue the bootup process.
The error message normally appears on the screen. See BIOS Error Messages later in this section
for descriptions of these messages.

Fatal errors are those which will not allow the system to continue the bootup procedure.

These fatal errors are usually communicated through a series of audible beeps. Each error message
has its own specific beep code, defined by the number of beeps following the error detection. The
following table lists the errors which are communicated audibly.

All errors listed, with the exception of #8, are fatal errors.

Count Message Description

Beep

1 Refresh Failure The memory refresh circuitry of the processor

board is faulty.

2 Parity Error A parity error was detected in the base memory

(the first block of 64KB) of the system.

3 Base 64KB A memory failure occurred within the

Memory Failure first 64KB of memory.

4 Timer Not Operational

A memory failure occurred within the first 64KB
of memory, or Timer #1 on the processor board has
failed to function properly.

5 Processor Error The CPU (Central Processing Unit) on the

processor board has generated an error.

6 8042 Gate A20 Failure The keyboard controller (8042) contains the Gate

A20 switch which allows the CPU to operate in
protected mode. This error message means that the
BIOS is not able to switch the CPU into protected
mode.

Manual Number: 40110-005-2 Page 81

Beep Count Message Description

7 Processor Exception Interrupt Error

The CPU on the processor board has generated an
exception interrupt.

8 Display Memory The system video adaptor is either missing or

Read/Write Error its memory is faulty. Note: This
is not a fatal error.

9 ROM Checksum Error The ROM checksum value does not match the

value encoded in the BIOS.

10 CMOS Shutdown

Register Read/Write
Error The shutdown register for the CMOS RAM has

failed.

11 Cache Memory Bad;

Do

Not Enable Cache The cache memory test failed. Cache memory is

disabled.

Do

not press <Ctrl> <Alt> <Shift> <+> to

enable cache memory.

BIOS Error Messages

If a nonfatal error occurs during the POST routines performed each time the system is powered on,
the error message will appear on the screen in the following format:

ERROR Message Line 1
ERROR Message Line 2
Press F1 to Resume

Note the error message and press the <F1> key to continue with the bootup procedure.

Note: If the “W ait for ‘F1’ If Any Error” option in the Advanced Setup portion of the BIOS Setup

Program has been set to Disabled, the “Press F1 to Resume” prompt will not appear on the
third line.

For most of the error messages, there is no ERROR Message Line 2. Generally, for those messages
containing an ERROR Message Line 2, the text will be “RUN SETUP UTILITY.” Pressing the
<F1> key will invoke the BIOS Setup Utility.

A description of each error message appears below. The errors are listed in alphabetical order, not
in the order in which they may occur.

Manual Number: 40110-005-2Page 82

Message Description

8042 Gate-A20 Error The gate-A20 portion of the keyboard controller (8042) has failed

to operate correctly. Replace the 8042 chip.

Address Line Short! An error has occurred in the address decoding circuitry of the

processor board.

C: Drive Error The BIOS is not receiving any response from hard disk drive C:.

Check Standard Setup using the BIOS Setup Utility to see if the
correct hard disk drive has been selected.

C: Drive Failure The BIOS cannot get any response from hard disk drive C:.

It may be necessary to replace the hard disk.

Cache Memory Bad, Cache memory is defective.
Do Not Enable Cache!

CH-2 Timer Error Most AT standard system boards include two timers. An error with

Timer#1 is a fatal error, explained in BIOS Beep Codes earlier
in this section. If an error occurs with Timer#2, this error
message appears.

CMOS Battery State Low There is a battery in the system which is used for storing the CMOS

values. This battery appears to be low in power and needs to be
replaced.

CMOS Checksum Failure After the CMOS values are saved, a checksum value is generated

to provide for error checking. If the previous value is different from
the value currently read, this error message appears. To correct the
error, run the BIOS Setup Utility.

CMOS Display Type
Mismatch The type of video stored in CMOS does not match the type detected

by the BIOS. Run the BIOS Setup Utility to correct the error.

CMOS Memory Size
Mismatch If the BIOS finds the amount of memory on the system board to be

different from the amount stored in CMOS, this error message is
generated. Run the BIOS Setup Utility to correct the error.

CMOS System The values stored in the CMOS are either corrupt or nonexistent.
Options Not Set Run the BIOS Setup Utility to correct the error.

Manual Number: 40110-005-2 Page 83

Message Description

CMOS Time & Date Not Set Use Standard Setup in the BIOS Setup Utility to set the date

and time of the CMOS.

D: Drive Error The BIOS is not receiving any response from hard disk

drive D:. Check Standard Setup using the BIOS Setup
Utility to see if the correct hard disk drive has been
selected.

D: Drive Failure The BIOS cannot get any response from hard disk drive D:.

It may be necessary to replace the hard disk.

Diskette Boot Failure The disk used to boot up in floppy drive A: is corrupt,

which means it cannot be used to boot up the system. Use
another boot disk and follow the instructions on the screen.

Display Switch Not Proper Some systems require that a video switch on the processor

be set to either color or monochrome, depending upon the
type of video being used. To correct this situation, set the
switch properly after the system is powered off.

DMA Error An error has occurred in the DMA controller on the

processor board.

DMA #1 Error An error has occurred in the first DMA channel on the

processor board.

DMA #2 Error An error has occurred in the second DMA channel on the

processor board.

FDD Controller Failure The BIOS is not able to communicate with the floppy disk

drive controller. Check all appropriate connections after
the system is powered off.

HDD Controller Failure The BIOS is not able to communicate with the hard disk

drive controller. Check all appropriate connections after
the system is powered off.

INTR #1 Error Interrupt channel #1 has failed the POST routine.

INTR #2 Error Interrupt channel #2 has failed the POST routine.

Invalid Boot Diskette The BIOS can read the disk in floppy drive A:, but it cannot

boot up the system with it. Use another boot disk and
follow the instructions on the screen.

Manual Number: 40110-005-2Page 84

Message Description

KB/Interface Error The BIOS has found an error with the keyboard connector

on the processor board.

Keyboard Error The BIOS has encountered a timing problem with the

keyboard. The Keyboard option in the Standard Setup
portion of the BIOS Setup Utility may be set to Not
Installed, which will cause the BIOS to skip the keyboard
POST routines.

Keyboard Is Locked. The keyboard lock on the system is engaged. It must be
Unlock it. unlocked to continue the bootup procedure.

No ROM BASIC This error occurs when a proper bootable sector cannot be

found on either floppy disk drive A: or hard disk drive C:.
The BIOS will try at this point to run ROM Basic, and the
error message is generated when the BIOS does not find it.

Off Board Parity Error The BIOS has encountered a parity error in memory

installed on an adapter card in an I/O (Bus) expansion slot.
The message appears as follows:

OFF BOARD PARITY ERROR;
ADDR (HEX) = (XXXX);

where XXXX is the address (in hexadecimal) at which the
error has occurred. “Off Board” means that it is part of the
memory installed via an expansion card in an I/O (Bus)
slot, as opposed to memory attached directly to the processor
board.

On Board Parity Error The BIOS has encountered a parity error in memory

installed on the processor board. The message appears as
follows:

ON BOARD PARITY ERROR;
ADDR (HEX) = (XXXX);

where XXXX is the address (in hexadecimal) at which the
error has occurred. “On Board” means that it is part of the
memory attached directly to the processor board, as opposed
to memory installed via an expansion card in an I/O (Bus)
slot.

Parity Error ???? The BIOS has encountered a parity error with some memory

in the system, but it is not able to determine the address of
the error.

Manual Number: 40110-005-2 Page 85

ISA BIOS NMI Handler Messages

The ISA NMI (non-maskable interrupt) messages are described below.

Message Description

Memory Parity Error Memory failed. The message appears as follows:

MEMORY PARITY ERROR AT XXXXX ;

where XXXXX is the address (in hexadecimal) at which
the error has occurred. If the memory location cannot be
determined, the message is “Memory Parity Error ????”

I/O Card Parity Error An expansion card failed. The message appears as follows:

I/O PARITY ERROR AT XXXXX ;

where XXXXX is the address (in hexadecimal) at which
the error has occurred. If the address cannot be determined,
the message is “I/O Card Parity Error ????”

DMA Bus Time-Out A device has driven the bus signal for more than 7.8

microseconds.

Port 80 Codes

The following codes are presented on Port 80H as the BIOS performs its reset procedure.

Code Description

Uncompressed Initialization Code Checkpoints

D0 NMI is disabled. Power-on delay starting. Initialization code checksum to be

verified next.

D1 Initializing DMA controller, performing keyboard controller BAT test, starting

memory refresh and entering 4GB flat mode next.
D3 Starting memory sizing next.
D4 Returning to real mode. Executing any OEM patches and setting stack next.

D5 Passing control to uncompressed code in shadow RAM at E000:0000H. Initialization

code copied to segment 0 and control to be transferred to segment 0.
D6 Control in segment 0. Checking if <Ctrl> + <Home> was pressed and verifying

system BIOS checksum. If <Ctrl> + <Home> was pressed or system BIOS

checksum is bad, going to checkpoint code E0H next. Otherwise, going to checkpoint

code D7H.
D7 Main BIOS runtime code to be decompressed and control to be passed to main BIOS

in shadow RAM. Boot Block Recovery Code Checkpoints:
E0 Onboard floppy controller initialized, if any. Beginning base 512KB memory test

next.
E1 Initializing interrupt vector table next.
E2 Initializing DMA and interrupt controllers next.

Manual Number: 40110-005-2Page 86

Code Description

E6 Enabling floppy drive controller and timer IRQ’s. Enabling internal cache memory.
ED Initializing floppy drive.

EE Looking for floppy diskette in drive A:. Reading first sector of diskette.
EF Read error occurred while reading floppy drive in drive A:.
F0 Searching for AMIBOOT.ROM file in root directory.
F1 AMIBOOT.ROM file not in root directory.
F2 Reading and analyzing floppy diskette FAT to find clusters occupied by

AMIBOOT.ROM file.
F3 Reading AMIBOOT.ROM file next, cluster by cluster.
F4 AMIBOOT.ROM file not correct size.
F5 Disabling internal cache memory next.
FB Detecting type of flash ROM next.
FC Erasing flash ROM next.
FD Programming flash ROM next.
FF Flash ROM programming successful. Restarting system BIOS next.

Runtime code is uncompressed in F000 shadow RAM.

03 NMI is disabled. Checking for soft reset/power-on next.
05 BIOS stack has been built. Disabling cache memory next.
06 Uncompressing POST code next.
07 Initializing CPU and CPU data area next.
08 CMOS checksum calculation to be done next.
0A CMOS checksum calculation done. Initializing CMOS status register for date and

time next.
0B CMOS status register initialized. Next, performing any required initialization

before keyboard BAT command issued.
0C Keyboard controller input buffer free. Issuing BAT command to keyboard controller

next.
0E Keyboard controller BAT command result verified. Performing any necessary

initialization after keyboard controller BAT test next.
0F Initialization after keyboard controller BAT command test done. Keyboard

command byte to be written next.
10 Keyboard controller command byte is written. Issuing Pin 23,24 blocking/unblocking

command next.
11 Checking if <End> or <Ins> keys were pressed during power-on next. Initializing

CMOS RAM if the “Initialize CMOS RAM in every boot” AMIBIOS POST option

was set in AMIBCP or the <End> key was pressed.
12 Disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2 next.

13 Video display disabled and port B initialized. Initializing chipset next.
14 8254 timer test to begin next.
19 8254 timer test over. Starting memory refresh test next.
1A Memory refresh line is toggling. Checking 15 microsecond on/off time next

Manual Number: 40110-005-2 Page 87

Code Description

23 Reading 8042 input port and disabling MEGAKEY Green PC feature next. Making

BIOS code segment writable and performing any necessary configuration before
initializing the interrupt vectors.

24 Configuration required before interrupt vector initialization complete. Interrupt

vector initialization about to begin.

25 Interrupt vector initialization done. Clearing password if POST diagnostic switch

is on.
27 Any initialization before setting video mode to be done next.
28 Initialization before setting video mode is complete. Configuring monochrome

mode and color mode settings next.
2A Bus initialization (system, static, output devices) to be done next, if present. (See

end of Port 80H Codes for details of different buses.)
2B Passing control to video ROM to perform any required configuration before video

ROM test
2C All necessary processing before passing control to video ROM is done. Looking for

video ROM next and passing control to it.
2D Video ROM has returned control to BIOS POST. Performing any required

processing after video ROM had control.
2E Completed post-video ROM test processing. If EGA/VGA controller not found,

performing display memory read/write test next.
2F EGA/VGA controller not found. Display memory read/write test about to begin.

30 Display memory read/write test passed. Looking for retrace checking next.
31 Display memory read/write test or retrace checking failed. Performing alternate

display memory read/write test next.
32 Alternate display memory read/write test passed. Looking for alternate display

retrace checking next.
34 Video display checking over. Setting display mode next.
37 Display mode set. Displaying power-on message next.
38 Initializing bus (input, IPL, general devices) next, if present. (See end of Port 80H

Codes for details of different buses.)
39 Displaying bus initialization error messages. (See end of Port 80H Codes for details

of different buses.)
3A New cursor position read and saved. Displaying “Hit <DEL>” message next

3B “Hit <DEL>” message displayed. Protected mode memory test about to start.
40 Preparing descriptor tables next.

42 Descriptor tables prepared. Entering protected mode for memory test next.
43 Entered protected mode. Enabling interrupts for diagnostics mode next.

44 Interrupts enabled (if diagnostics switch is on). Initializing data to check memory

wraparound at 0:0 next
45 Data initialized. Checking for memory wraparound at 0:0 and finding total system

memory size next.
46 Memory wraparound test done. Memory size calculation done. Writing patterns to

test memory next.
47 Memory pattern written to extended memory. Writing patterns to base 640KB

memory next.

Manual Number: 40110-005-2Page 88

Code Description

48 Patterns written in base memory. Determining amount of memory below 1MB

memory next.

49 Amount of memory below 1MB found and verified. Determining amount of

memory above 1MB memory next.

4B Amount of memory above 1MB found and verified. Checking for soft reset and

clearing memory below 1MB for soft reset next. (If power-on situation, going to
checkpoint 4EH next.)

4C Memory below 1MB has been cleared via soft reset. Clearing memory above 1MB

next.

4D Memory above 1MB has been cleared via soft reset. Saving memory size next.

(Going to checkpoint 52H next.)

4E Memory test started, but not as result of soft reset. Displaying first 64KB memory

size next.

4F Memory size display started. Display is updated during memory test. Performing

sequential and random memory tests next.

50 Memory below 1MB has been tested and initialized. Adjusting displayed memory

size for relocation and shadowing next.

51 Memory size display adjusted for relocation and shadowing. Testing memory

above 1MB next.

52 Memory above 1MB has been tested and initialized. Saving memory size information

next.

53 Memory size information and CPU registers are saved. Entering real mode next.
54 Shutdown was successful. CPU in real mode. Disabling Gate A20 line, parity and

NMI next.

57 A20 address line, parity and NMI are disabled. Adjusting memory size depending

on relocation and shadowing next.

58 Memory size adjusted for relocation and shadowing. Clearing “Hit <DEL>”

message next.

59 “Hit <DEL>” message cleared. “Wait...” Message displayed. Starting DMA and

interrupt controller tests next.

60 DMA page register test passed. Performing DMA controller 1 base register test

next.

62 DMA controller1 base register test passed. Performing DMA controller 2 base

register test next.

65 DMA controller_2 base register test passed. Programming DMA controllers 1 and

2 next.

66 Completed programming DMA controllers 1 and 2. Initializing 8259 interrupt

controller next.
67 Completed 8259 interrupt controller initialization.
7F Extended NMI sources enabling in progress.
80 Keyboard test started. Clearing output buffer, checking for stuck keys. Issuing

keyboard reset command next.
81 Keyboard reset error or stuck key found. Issuing keyboard controller interface test

command next.

Manual Number: 40110-005-2 Page 89

Code Description

82 Keyboard controller interface test completed. Writing command byte and initializing

circular buffer next.

83 Command byte written, global data initialization completed. Checking for locked

key next.

84 Locked key checking over. Checking for memory size mismatch with CMOS RAM

data next.

85 Memory size check done. Displaying soft error and checking for pass- word or

bypassing Setup next.

86 Password checked. Performing any required programming before Setup next.
87 Programming before Setup complete. Uncompressing Setup code and executing

Setup utility next.

88 Returned from Setup program and screen is cleared. Performing any necessary

programming after Setup next.

89 Programming after Setup complete. Displaying power-on screen message next.
8B First screen message displayed. “Wait...” message displayed. Performing PS/2

mouse check and extended BIOS data area allocation check next.
8C Programming Setup options next.
8D Setup options are programmed. Resetting hard disk controller next.
8F Hard disk controller reset done. Configuring floppy drive controller next.

91 Floppy drive controller configured. Configuring hard disk drive controller next.
95 Initializing bus option ROM’s from C800 next. (See end of Port 80H Codes for

details of different buses.)
96 Initializing before passing control to adapter ROM at C800.
97 Initialization before C800 adapter ROM gains control completed. Adapter ROM

check next.
98 Adapter ROM had control and has returned control to BIOS POST. Performing any

required processing after option ROM returned control.
99 Any initialization required after option ROM test has completed. Configuring timer

data area and printer base address next.
9A Set timer and printer base addresses. Setting RS-232 base address next.
9B Returned after setting RS-232 base address. Performing any required initialization

before coprocessor test next.
9C Required initialization before coprocessor test is over. Initializing coprocessor

next.
9D Coprocessor initialized. Performing any required initialization after coprocessor

test next.
9E Initialization after coprocessor test is complete. Checking extended key board,

keyboard ID and Num Lock key next. Issuing keyboard ID command next.
A2 Displaying any soft errors next.

A3 Soft error display complete. Setting keyboard typematic rate next.
A4 Keyboard typematic rate set. Programming memory wait states next.
A5 Memory wait state programming over. Clearing screen and enabling parity and

NMI next.
A7 NMI and parity enabled. Performing any initialization required before passing

control to adapter ROM at E000H next.

Manual Number: 40110-005-2Page 90