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=========================================================================================
Icom, Icom Inc. and Icom logo are registered trademarks of Icom Incorporated (Japan) in the United states, the
United Kingdom, Germany, France, Spain, Russia and/or other countries.
Microsoft and Windows are registered trademarks of Microsoft Corporation in the U.S.A. and other countries.
Copyright 2004 Icom Inc.
=========================================================================================
2
SERVICE
MANUAL
VHF TRANSCEIVERS
INTRODUCTION
This service manual describes the latest service
information for the
TRANSCEIVERS
MODELCHANNEL SPACING SYMBOLFREQUENCY
IC–F33GT
IC–F34GT 12.5/20.0/25.0 kHzEUR-01136–174 MHz
IC–F33GS
IC–F34GS 12.5/20.0/25.0 kHzEUR-01136–174 MHz
To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
IC-F33GT/GS and IC-F34GT/GS VHF
at the time of publication.
15.0/30.0 kHzUSA-01136–174 MHz
12.5/25.0 kHzGEN-01136–174 MHz
15.0/30.0 kHzUSA-01136–174 MHz
12.5/25.0 kHzGEN-01136–174 MHz
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 8 V. Such a connection
could cause a fire or electric hazard.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the transceiver's front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
5030002760 LCD FX-2721 LCD IC-F33GT Main unit 5 pieces
8810009220 Screw BO 2x8 ZK IC-F33GT/GS Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 30 dB to 40 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.
Specifi cations are measured in accordance with EIA-152-C/204D, TIA-603 or EN 300 086.
All stated specifi cations are subject to change without notice or obligation.
1 Unscrew 1 nut A, and remove 2 knobs B, C.
2 Unscrew 2 screws D.
3 Unscrew 2 screws E.
4 Take off the chassis unit in the direction of the arrow.
5 Unplug the connector F from the chassis unit.
Chassis unit
E
A
B
C
F
D
REMOVING THE MAIN UNIT
•
1 Unscrew 2 nuts G, and remove the top plate H.
2 Remove the side plate I.
3 Unscrew 6 screws J.
4 Unsolder 8 points K, and remove the main shield.
5 Unsolder 2 points L, and take off the main unit in the
direction of the arrow.
Main shield
K
K
REMOVING THE PA UNIT
•
1 Unscrew 3 screws M.
2 Unsolder 4 points N, and take off the PA unit in the
direction of the arrow.
M
N
N
G
J
H
Chassis unit
L
J
Main unit
J
I
3 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (PA UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.
Received signals enter the antenna connector (CHASSIS;
J1) and pass through the low-pass filter (ANT unit; L801,
L802, C803). The filtered signals are passed through the
type antenna switching circuit (D701, D704, D706) and then
applied to the RF circuit.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the two-stage tunable bandpass filters (D19, D24, L7, L8,
C27, C369). The filtered signals are amplified at the RF
amplifier (Q5) and then passed through the another twostage tunable bandpass filters (D14, D15, L11, C39, C45)
to suppress unwanted signals. The filtered signals are
applied to the 1st mixer circuit.
D14, D15, D19 and D24 employ varactor diodes, that are
controlled by the CPU via the D/A converter (IC12), to track
the bandpass filter. These varactor diodes tune the center
frequency of an RF passband for wide bandwidth receiving
and good image response rejection.
λ
⁄4
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signal into fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
passes through a monolithic filter at the next stage of the
1st mixer.
The RF signals from the bandpass filter are mixed with the
1st LO signals, where come from the RX VCO circuit, at the
1st mixer circuit (Q6) to produce a 46.35 MHz 1st IF signal. The 1st IF signal is passed through a monolithic filter
(FI1) to suppress out-of-band signals. The filtered signal is
applied to the 2nd IF circuit after being amplified at the 1st
IF amplifier (Q7).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd
IF signal. The double-conversion superheterodyne system
(which convert receive signals twice) improves the image
rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q7) is applied to
the 2nd mixer section of the FM IF IC (IC9, pin 16), and is
mixed with the 2nd LO signal to be converted into a 450
kHz 2nd IF signal.
The FM IF IC (IC9) contains the 2nd mixer, limiter amplifier,
quadrature detector, active filter and noise amplifier circuits.
A 2nd LO signal (45.9 MHz) is produced at the PLL circuit
by tripling it’s reference frequency 15.3 MHz).
• 2ND IF DEMODULATOR CIRCUIT
87
Active
filter
"SQLC" signal from the
D/A converter IC
(IC12, pin 2)
AF signal "DET"
FM
detector
Noise
Limiter
amp.
X1
amp.
5
2nd IF filter
450 kHz
Noise
detector
RSSI
FI2
Noise
comparator
3
Mixer
45.9 MHz
2
Q22
×3
X2
15.3 MHz
IC9 TA31136FN
11109
12
"RSSI" signal to the CPU ( IC22, pin 50)
R5V
13
"NOIS" signal to the CPU (IC22, pin 75)
16
1st IF from the IF amplifier (Q7)
4 - 1
The 2nd IF signal from the 2nd mixer (IC9, pin 3) passes
through the ceramic filter (FI2) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier
section (IC9, pin 5) and applied to the quadrature detector
section (IC9, pins 10, 11) to demodulate the 2nd IF signal
into AF signals.
The demodulated AF signals are output from pin 9 (IC9) and
applied to the base band IC (IC14).
4-1-5 AF AMPLIFIER CIRCUIT (MAIN UNIT)
The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker. This transceiver employs the base
band IC which is composed of pre-amplifier, expander,
scrambler, MSK de-modulator, etc. at the AF amplifier section.
The AF signals from the FM IF IC (IC9, pin 9) are amplified
at the AF amplifier section in the base band IC (IC14, pin
23), and are then applied to the high-pass filter and low-
pass filter section of it.
The filtered signals pass through the high-pass filter to suppress unwanted harmonic components. The signals pass
through (or bypass) scrambler and expander sections. The
signals are amplified at the amplifier section in the base
band IC (IC14).
4-1-6 SQUELCH CIRCUITS (MAIN UNIT)
• NOISE SQUELCH
A squelch circuit cuts out AF signals when no RF signals
are received. By detecting noise components in the AF signals, the squelch circuit switches the AF amplifier controller.
A portion of the AF signals from the FM IF IC (IC9, pin 9)
are passed through the D/A converter (IC12, pins 1, 2). The
signals are applied to the active filter section in the FM IF
IC (IC9, pin 8). The active filter section filters and amplifies
noise components. The amplified signals are converted into
the pulse-type signals at the noise detector section. The
detected signals output from pin 13 (NOIS) via the noise
comparator section.
The “NOIS” signal from the FM IF IC is applied to the CPU
(IC22, pin 75). Then the CPU analyzes the noise condition
and outputs AF mute control signal from pin 84 to control
the squelch switch (Q502) as the “MUTE” signal.
• CTCSS AND DTCS
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone
is received, the tone squelch circuit mutes the AF signals
even when noise squelch is open.
The output signals from IC14 (pin 20) pass through the lowpass filter sector (IC23, pins 1, 2), and are then applied to
the AF amplifier (IC15, pin 8) via the AF volume (R315).
The power amplified AF signals are output from pin 10 and
applied to the internal speaker that is connected to J4 via [SP]
jack (J2).
• AF AND MIC AMPLIFIER CIRCUIT
"DET" AF signal
from FM IF IC (IC9, pin 9)
IC13
FM/PM switch
IC6
LPF
23
7
IC12
4
D/A converter
Base band IC
(IC14)
3
20
3
D12
FM mod.
A portion of the “DET” AF signals from the FM IF IC (IC9,
pin 9) pass through the low-pass filter (IC19, pin 5) to
remove AF (voice) signals, and are then applied to the
amplifier (IC19, pin 3). The amplified signals are applied to
the CTCSS or DTCS decoder in the CPU (IC22, pin 46) via
the “CDEC” line. The CPU outputs AF mute control signal
from pin 84 to control the squelch switch (Q502) as the
“MUTE” signal.
IC23
LPF
IC23
AMP
to TX VCO circuit
(Q16, D10, D13, D501)
AF
volume
IC15
AF
AMP
Speaker
Microphone
"CTCSS/DTCS" signal from
D/A conveter IC (IC12, pin 11)
"TONE" signal from CPU via low-pass
filter (IC22, pin 43)
4 - 2
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(MAIN UNIT)
The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.
This transceiver employs the base band IC which is composed of microphone amplifier, compressor, scrambler,
limiter, splatter filter, MSK modulator, etc. at the microphone
amplifier section.
The AF signals (MIC) from the microphone (MC1) are
applied to the amplifier (IC23, pins 6, 7). The amplified signals are amplified again at the microphone amplifier section
of the base band IC (IC14, pins 3). The amplified signals are
passed through or bypass the compressor, scrambler sections of IC14, and are then passed through the high-pass,
limiter amplifier, splatter filter sections of IC14.
The filtered AF signals from the base band IC (pin 6) are
applied to the FM/PM switch (IC13, pins 6, 7), and pass
through the low-pass filter (IC6, pins 1, 2). The filtered signals are applied to the D/A converter (IC12, pin 4). The output signals from the D/A converter (IC12, pin 3) are applied
to the modulation circuit (D12).
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC12, pin 3) change
the reactance of varactor diode (D12) to modulate the oscillated signal at the TX VCO circuit (Q16, D10, D13, D501).
The modulated VCO signal is amplified at the buffer amplifiers (Q15, Q29) and is then applied to the drive amplifier
circuit via the T/R switch (D16).
The CTCSS/DTCS signals (“CENC0”, “CENC1”, ”CENC2")
from the CPU (IC22, pins 13, 15, 16) are combined at the
resistors (R222–R224) and are then pass through the lowpass filter (IC6, pins 12, 14). The filtered signals are applied
to the D/A converter (IC12, pin 12) via the “TONC” line. The
output signals from the D/A converter (IC12, pin 11) are
mixed with the filtered Mic audio signals.
The mixed signals are passed through the D/A converter
(IC12, pin 3, 4), and are then applied to the D12 in the TX
VCO circuit.
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(PA UNIT)
The drive/power amplifier circuits amplify the TX VCO oscillating signal to an output power level.
The signal from the TX VCO circuit passes through the T/R
switch (MAIN unit; D16), and is amplified at the YGR (Q704),
drive (Q702), power (Q701) amplifiers to obtain 5 W of RF
power (at 7.2 V DC).
The amplified signal is passed through the low-pass filter
(L703, L704, C708, C711, C768), power detector (D702,
D703), antenna switching circuit (D701) and another lowpass filters (PA unit; L709, C744, C746, C769 / ANT unit;
L801, L802, C802, C803, C807), and is then applied to the
antenna connector (CHASSIS unit; J1).
The bias voltage of the drive (Q702) and power (Q701)
amplifiers are controlled by the APC circuit.
4-2-4 APC CIRCUIT (PA AND MAIN UNITS)
The APC circuit protects the drive and power amplifiers from
a mismatched output load and selects output power of HIGH
or LOW.
The power detector circuit (PA unit; D702, D703) detects the
transmit power output level and converts it into DC voltage.
The output voltage is at a minimum level when the antenna
impedance is matched with 50 Ω and is increased when it is
mismatched.
The detected voltage is applied to the differential amplifier
(MAIN unit; IC2; pin 3), and the “T2” signal from the D/A converter (MAIN unit; IC12, pin 23), controlled by the CPU (MAIN
unit; IC22), is applied to the other input for reference. When
antenna impedance is mismatched, the detected voltage
exceeds the power setting voltage. Then the output voltage
of the differential amplifier (MAIN unit; IC2, pin 4) controls
the input bias voltage of the drive (PA unit; Q702) and power
(PA unit; Q701) amplifiers to reduce the output power.
• APC CIRCUIT
VCC
T5V
RF signal
from PLL circuit
T2
TMUT
APC control circuit
IC501
PA unit
Q704
YGR
amp.
–
IC2
APC
amp.
+
Q702
Driver
amp.
Powe r
amp.
Q701
LPF
D702
ANT
SW
D701
LPF
to ANT unit
D703
4 - 3
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX and RX VCO circuits (Q16,
Q17, D9–D11, D13, D500, D501). The oscillated signal is
amplified at the buffer amplifier (Q15). The output signal frequency is doubled at Q14, and is then applied to the PLL IC
(IC21, pin 6) after being passed through the bandpass filter
(L32, C205, C507).
4-3-2 VCO CIRCUITS (MAIN UNIT)
The VCO circuits contains a separate RX VCO (Q17, D9,
D11, D500) and TX VCO (Q16, D10, D13, D501). The oscillated signal is amplified at the buffer amplifiers (Q15, Q29)
and is then applied to the T/R switch (D16, D17). Then the
receive 1st LO (Rx) signal is applied to the 1st mixer (Q6)
and the transmit (Tx) signal to the YGR amplifier circuit (PA
unit; Q704).
A portion of the signal from the buffer amplifier (Q15) is fed
back to the PLL IC (IC21, pin 6) via the doubler circuit (Q14)
as the comparison signal.
Q500, D502 and D503 switch the filtering frequencies
between TX and RX which is controlled by R5V.
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The applied
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the reference frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
• PLL CIRCUIT
RX VCO
Q17, D9, D11, D500
TX VCO
Q16, D10, D13, D501
"LVIN" signal
to the CPU
(IC22, pin 49)
Buffer
Q21
Loop
filter
4-4 POWER SUPPLY CIRCUIT
4-1-1 MAIN UNIT VOLTAGE
LINEDESCRIPTION
VCCThe voltage from the connected battery pack.
Common 5 V converted from the VCC line at the
+5V
S5V
R5V
T5V
Buffer
Q15
IC21 LMX2352
+5 regulator circuit (IC17). The output voltage is
supplied to the buffer amplifiers (Q21), PLL IC
(IC21) etc.
Common 5 V converted from the VCC line at the
S5 regulator circuit (Q26–Q28). The output voltage is supplied to the ripple fi lter (Q20), etc.
Receive 5 V converted from the S5V line at the
R5 regulator circuit (Q25). The output voltage is
supplied to the tripler (Q22), FM IF IC (IC9), IF
amplifi er (Q7), 1st mixer (Q6), RF amplifi er (Q5),
etc.
Transmit 5 V converted from the S5V line at the
T5 regulator circuit (Q24). The output voltage is
supplied to the APC amplifi er (IC2), PA unit, etc.
Buffer
Q29
×2
Q14
D17
D16
BPF
to 1st mixer circuit
to transmitter circuit
45.9 MHz 2nd LO
signal to the FM IF IC
(IC9, pin 2)
Tripler
3
Q22
Phase
4
detector
Programmable
divider
10
Programmable
counter
X2
15.3 MHz
4 - 4
Prescaler
Shift register
6
14
15
16
SCK
SO
PLST
4-5 OTHER CIRCUITS
4-5-1 COMPANDER CIRCUIT (MAIN UNIT)
IC-F33GT/GS/F34GT/GS have compander circuit which can
improve S/N ratio and become wide dynamic range. The circuit is composed in the base band IC (IC14).
(1) IN CASE OF TRANSMITTING
The audio signals from the microphone are applied to the
base band IC (IC14, pin 3) via microphone amplifier (IC23).
The signals are amplified at the amplifier section, and are
then applied to the compressor circuit to compress the audio
signals. The signals pass through (or bypass) scrambler section, and are then applied to the limiter section after being
passed through the high-pass filter. The filtered signals pass
through the splatter filter section, and are then applied to the
modulation circuit (D12) via the FM/PM switch (IC13), lowpass filter (IC6) and D/A converter (IC12).
(2) IN CASE OF RECEIVING
The demodulated AF signals from the IF IC are applied to
the amplifier section in base band IC (IC14, pin 23), and
then pass through the low-pass and high-pass filter section to suppress unwanted signals. The filtered signals pass
through (or bypass) scrambler section, and are then applied
to the expander circuit to expand AF signals. The signals are
applied to the base band IC’s amplifier section (IC14, pins
19, 20), and are then applied to the AF amplifier circuit.
4-6 PORT ALLOCATIONS
4-6-1 D/A CONVERTOR IC (IC12)
Pin
Number
10BAL
14TLVA
15RLVA
22
23T2
Port
name
T1
Description
Outputs the modulation balance level
control signal. The signal is applied to
the buffer amplifi er (IC24, pin 1).
Outputs the TX VCO lock voltage
control signal.
Outputs the RX VCO lock voltage
control signal.
Outputs the bandpass filter tuning
control signal . The output signal is
applied to the bandpass fi lters (D19,
D240).
• Outputs the bandpass filter tuning
control signal . The output signal is
applied to the bandpass fi lters (D14,
D15).
• Outputs the TX control signal . The
output signal is applied to the APC
amplifi er (IC2, pin 1).
• BASE BAND IC BLOCK DIAGRAM
Pre-
emphasis
Modulator
Demodulator
MSK
MSK
MTDT
MTCK
Com-
pressor
RX
LPF
MSK
BPF
TXA1
RXA1
Control
Register
VR1
(HPF)
VR3
(HPF)
3TXIN
23RXIN
21SDEC
10
9
14MDIR
13MSCK
11MDIO
12MRDF
TX/RX
HPF
Scrambler/
De-scrambler
LimiterSplatterVR2
De-
emphasis
ExpanderVR4
RXA2
SMF
7 MOD
18
19
20 SIGNAL
4 - 5
4-6-2 CPU (MAIN unit; IC22)
Pin
number
13, 15, 16CENC0–
29REF
30PLST
34PMFM
35MDIO
36MSCK
37MDIR
38MTCK
39MTDT
40MRDF
41DAST
43SENCOutput single tone encoder signal.
44BEEPOutputs beep audio signals.
45SDEC
46CDEC
48BATV
49LVINInput port for the PLL lock voltage.
50RSSI
51TEMP
69CSFT
70AFON
Port
name
CENC2
Description
Output the CTCSS/DTCS signals.
Outputs the reference oscillator correcting voltage. The voltage is applied
to the buffer amplifi er (IC24, pin 3)
Outputs strobe signals to the PLL IC
(IC21, pin 16).
Outputs the FM/PM modulation
switching signal to the FM/PM switch
(IC13, pin 5).
I/O port for the serial data signals
from/to the base band IC (IC14,
pin 11).
Outputs clock signal for the base
band IC (IC14, pin 13).
Outputs serial data control signal to
the base band IC (IC14, pin 14).
Input port for transmitting MSK clock
signal from the base band IC (IC14,
pin 9).
Outputs MSK data for transmitting to
the base band IC (IC14, pin 10).
Input port for the receiving MSK detection signal from the base band IC
(IC14, pin 12).
Outputs strobe signals to the D/A
convertor (IC12, pin 6).
Input port for single tone decode
signal from the base band IC (IC14,
pin 21).
Input port for CTCSS/DTCS signal
from the amplifi er (IC19, pin 1).
Input port for the detect signal for
connecting battery pack’s voltage.
Input port for the S-meter signal from
the FM IF IC (IC9, pin 12).
Input port for the transceiver’s internal
temperature detecting signal.
Outputs shift signal for reference oscillator’s frequency.
Outputs audio control signal.
Low: While outputs audio signals
from the speaker.
Pin
Number
74PTT
75NOIS
76SO
78SCK
79CLIInput port for the cloning data signal.
80CLOOutputs the cloning data signal.
82ESDA
84MUTE
85ESCL
86S5C
87T5C
88R5C
89TMUT
Port
name
Description
Input port for the PTT switch detection signal.
Low: While the PTT switch is
pushed.
Input port for the noise signal from
the FM IF IC (IC9, pin 13).
Outputs serial data to the PLL IC
(IC21, pin 15) and D/A convertor
(IC12, pin 8).
Outputs serial clock signal to the PLL
IC (IC21 pin 14), D/A convertor (IC12,
pin 7), etc.
I/O port for data signals from/to the
EEPROM (IC10, pin 5).
Outputs AF control signal .
Low: While Squelch ON.
Outputs clock signal to the EEPROM
(IC10, pin 6).
Outputs the S5 regulator (Q26–Q28)
control signal.
Low: While the S5 regulator out-
puts 5 V voltage.
Outputs the T5 regulator (Q24) control signal.
Low: While transmitting.
Outputs the R5 regulator (Q25) control signal.
Low: While receiving.
Outputs the transmitting mute switch
control signal to the mute switch
(Q 501).
High: While muting.
4 - 6
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION
When adjusting IC-F33GT/F33GS/F34GT/F34GS, the optional CS-F33G ADJ
OPC-478
CLONING CABLE
(RS-232C type), OPC-478U
CLONING CABLE
(USB type) and a JIG CABLE (see illustration at page 5-3)
are required.
▄
REQUIRED TEST EQUIPMENT
EQUIPMENTGRADE AND RANGEEQUIPMENTGRADE AND RANGE
DC power supply
FM deviation meter
Frequency counter
Digital multimeterInput impedance : 10 MΩ/V DC or better AC millivoltmeterMeasuring range: 10 mV–10 V
RF power meter
▄
SYSTEM REQUIREMENTS
Output voltage
Current capacity
Frequency range
Measuring range
Frequency range
Frequency accuracy
Sensitivity
Measuring rang
Frequency range
Impedance
SWR
• Microsoft® Windows® 98/98SE/Me/2000
• RS-232C serial port (D-sub 9 pin)
• USB port
: 7.2 V DC
: 5 A or more
: DC–800 MHz
: 0 to ±10 kHz
: 0.1–300 MHz
: ±1 ppm or better
: 100 mV or better
: 1–10 W
: 100–800 MHz
: 50
Ω
: Better than 1.2 : 1
Audio generator
Attenuator
Standard signal
generator (SSG)
Oscilloscope
▄
STARTING SOFTWARE ADJUSTMENT
Connect the transceiver and PC with the OPC-478/U and
q
JIG CABLE.
Turn the transceiver power ON.
w
Boot up Windows, and click the program group ‘CS-F33G
e
ADJ’ in the ‘Programs’ folder of the [Start] menu, then
▄
ADJUSTMENT SOFTWARE INSTALLATION
Boot up Windows.
q
- Quit all applications when Windows is running.
Insert the cloning software CD into the appropriate CD
w
CS-F33G ADJ’s window appears.
Click ‘Connect’ on the CS-F33G’s window, then appears
r
the transceiver’s adjustment screen.
Set or modify adjustment data as desired.
t
drive.
Select ‘Run’ from the [Start] menu.
e
Type the setup program name using the full path name,
r
then push [Enter] key.
(For example; D:\Setup.exe)
Follow the prompts.
t
Program group ‘CS-F33G ADJ’ appears in the ‘Programs’
y
folder of the [Start] menu.
▄
BEFORE STARTING SOFTWARE ADJUSTMENT
• ADJUSTMENT FREQENCY LIST
CHFREQUENCYADJUSTMENT ITEM
1155.000 MHz
2155.000 MHz
Program the adjustment frequencies into the transceiver
using with the CS-F33G before starting the software adjust-
3155.000 MHz
ment. Otherwise, the transceiver can not start software adjustment.
CAUTION!: BACK UP the originally programmed mem-
ory data in the transceiver before program-
4155.000 MHz
5136.000 MHZ
ming the adjustment frequencies.
When program the adjustment frequencies into
the transceiver, the transceiver’s memory data
6155.000 MHz
will be overwritten and lose original memory
data at the same time.
7174.000 MHz
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
8155.000 MHz
ADJUSTMENT SOFTWARE
Frequency range
Measuring range
Power attenuation
Capacity
Frequency range
Output level
Frequency rang
Measuring range
TX power
Bandwidth
TX power
Bandwidth
TX power
Bandwidth
TX power
Bandwidth
TX power
Bandwidth
TX power
CTCSS
DTCS
Bandwidth
TX power
Bandwidth
TX power
Bandwidth
: High
: Wide
: Low 2
: Wide
: Low
: Wide
: High
: Narrow
: High
: Wide
: High
: 151.4 Hz
: 007
: Wide
: High
: Wide
: High
: Middle
(Rev. 1.0 or later),
: 300–3000 Hz
: 1–500 mV
: 20 or 30 dB
: 10 W
: 100–800 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
: DC–20 MHz
: 0.01–20 V
5 - 1
• CS-F33G ADJ'S SCREEN EXAMPLE
q
w
t
y
i
!0
!2
!4
!6
!8
u
o
!1
!3
!7
!9
r
!5
e
NOTE:
q: Transceiver's connection state
w: Reload adjustment data
e: Receive sensitivity measurement
r: Connected DC voltage measurement
t: PLL lock voltage measurement
y: Operating channel select
u: RF output power
i: FM modulation balance (Narrow)
o: FM deviation (Narrow)
!0: FM deviation (Wide/Middle)
The above values for settings are example only.
Each transceiver has its own specific values for each setting.
!1: CTCSS/DTCS deviation
!2: Squelch level
!3: Reference frequency
!4: Receive sensitivity (automatic)
!5: PLL lock voltage for RX (automatic)
!6: PLL lock voltage for TX (automatic)
!7: PLL lock voltage for RX (manual)
!8: PLL lock voltage for TX (manual)
!9: S-meter adjustment
5 - 2
• CONNECTION
AC millivoltmeter
Standard signal generator
0.1 µV to 32 mV
(−127 dBm to −17 dBm)
CAUTION!
DO NOT transmit while
an SSG is connected to
the antenna connector.
FM
deviation meter
Attenuator
20 dB or 30 dB
RF power meter
0.1−10 W/50 Ω
Frequency
counter
to the antenna connector
To [SP]
To [MIC]
JIG cable
Audio generator
OPC-478 (RS-232C type)
to RS-232C port
OPC-478U (USB type)
to USB port
PC
SINAD meter
Speaker (8 Ω)
• JIG CABLE
To IC-F33G/F34G
[SP] jack
IC-F33G/F34G
3-conductor 3.5(d) mm (
JIG cable
1
⁄8") plug
(CLONE)
(SP + )
(SPE − )
(GND)
OPC-478/OPC478U
5 - 3
5-2 SOFTWARE ADJUSTMENT (TRANSMITTING)
Select an operation using [↑] / [↓]keys, then set specifi ed value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENTADJUSTMENT CONDITION
PLL LOCK
VOLTAGE
[LV (RX LVA)]
[LV (TX LVA)]
1 • Operating Channel : CH7
• Receiving
2 • Operating Channel : CH7
• Transmitting
CONVENIENT:
The PLL lock voltage can be adjustment automatically.
Set the cursor to "RX LVA"/"TX LVA" and then push [ENTER] key.
3 • Operating Channel : CH5
• Receiving
4 • Operating Channel : CH5
• Transmitting
REFERENCE
FREQUENCY
[REF]
OUTPUT
POWER
[Power (Hi)]
[Power (L2)]2 • Operating Channel : CH2
[Power (L1)]3 • Operating Channel : CH3
MODULATION
BALANCE
[BAL]
FM
DEVIATION
[MOD N]
(Narrow)
[MOD Ratio]
(Wide)
[MOD Ratio]
(Middle)
(F34G only)
CTCSS/DTCS
DEVIATION
[CTCSS/DTCS]
1 • Operating Channel : CH7
• Connect the RF power meter or 50 Ω dummy
load to the antenna connector.