Icom IC-2800h Service Manual

DUAL BAND FM TRANSCEIVER

iC-2800h

INTRODUCTION

DANGER

This service manual describes the latest service information for the IC-2800H FM TRANSCEIVER at the time of publication.

MODEL VERSION SYMBOL

Europe

Italy

IC-2800H

To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation.

U.S.A.

S. E. Asia

EUR

ITA USA SEA

CSAC. S. America

NEVER connect the transceiver to an AC outlet or to a DC

power supply that uses more than 16 V. Such a connection could cause a fire hazard and/or electric shock.

DO NOT expose the transceiver to rain, snow or any liq-

uids.

DO NOT reverse the polarities of the power supply when

connecting the transceiver.

DO NOT apply an RF signal of more than 20 dBm (100

mW) to the antenna connector. This could damage the transceiver’s front end.

ORDERING PARTS

Be sure to include the following four points when ordering replacement parts:

1. 10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required

1110002750 S.IC TA75S01F IC-2800H MAIN UNIT 1 piece 8810008450 Screw M4 × 8 ZK IC-2800H CHASSIS 6 pieces

Addresses are provided on the inside back cover for your convenience.

REPAIR NOTES

1. Make sure a problem is internal before disassembling the transceiver.

2. DO NOT open the transceiver until the transceiver is disconnected from its power source.

3. DO NOT force any of the variable components. Turn them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An insu lated tuning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the transceiver is defective.

6. DO NOT transmit power into a signal generator or a sweep generator.

7. ALWAYS connect a 50 dB or 60 dB attenuator between the transceiver and a deviation meter or spectrum analyser when using such test equipment.

8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPTION

4 - 1 RECEIVER CIRCUITS ................................................................................................... 4 – 1

4 - 2 TRANSMITTER CIRCUITS ........................................................................................... 4 – 3

4 - 3 PLL CIRCUIT.................................................................................................................. 4 – 4

4 - 4 POWER SUPPLY CIRCUITS ........................................................................................ 4 – 5

4 - 5 CPU PORT ALLOCATIONS ........................................................................................... 4 – 5

SECTION 5 ADJUSTMENT PROCEDURES

5 - 1 PREPARATION............................................................................................................... 5 – 1

5 - 2 PLL AND TRANSMITTER ADJUSTMENTS................................................................... 5 – 2

5 - 3 RECEIVER ADJUSTMENT ............................................................................................ 5 – 4

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS AND DISASSEMBLY

SECTION 8 SEMI-CONDUCTOR INFORMATION

SECTION 9 BOARD LAYOUTS

9 - 1 CONTROL UNIT............................................................................................................. 9 – 1

9 - 2 MAIN UNIT...................................................................................................................... 9 – 3

SECTION 10 BLOCK DIAGRAM

SECTION 11 VOLTAGE DIAGRAM

11 - 1 CONTROL UNIT.............................................................................................................11 – 1

11 - 2 MAIN UNIT.....................................................................................................................11 – 2

M GENERAL

• Frequency range :

*1Guaranteed 144.000 – 148.000 MHz only *2Guaranteed 430.000 – 440.000 MHz only; *3Guaranteed 440.000 – 450.000 MHz only

• Mode : FM, AM (118.0 – 135.995; Rx only)

• Nomber of memory channel : 232 (incl. 6 pairs of scan edges, 10 log, 10 repeater and 2 call channels)

• Usable temperature range : –10˚C to +60˚C; +14˚F to +140˚F

• Frequency resolution : 5, 10, 12.5, 15, 20, 25, 30 and 50 kHz

• Frequency stability : ±10 ppm (–10˚C to +60˚C; +14˚F to +140˚F)

• Power supply requirement : 13.8 V DC ±15 % (negative ground)

• Current drain

(at 13.8 V DC) : Receive Standby (squelched) 1.2 A

Max. audio 1.5 A

Transmit at VHF 50 W/UHF 35 W 12.0 A/11.0 A

at 25 W/25 W (TPE version) 8.0 A

• Antenna connector : SO-239 (50 Ω)

• DATAconnector : Mini DIN 6 pin

• External VIDEO input : PHONO [RCA (75 Ω)]

• Dimensions : Controller 140(W)

×70(H)×34(D) mm; 51⁄2(W)×23⁄4(H)×111⁄32(D) inch

(projections not included) Main unit 140(W)×40(H)×165.8(D) mm; 5

⁄2(W)×19⁄16(H)×617⁄32(D) inch

• Weight : Controller 290 g; 10.2 oz Main unit 1.15 kg; 2 lb 9 oz

M TRANSMITTER

• Output power : High VHF 50 W/UHF 35 W Mid-H approx. 20 W Mid-L approx. 10 W Low approx. 5 W

• Modulation system : Variable reactance frequency

• Maximum frequency deviation: ±5.0/±2.5* kHz

*[EUR] and [ITA] versions only

• Spurious emissions : Less than –60 dB

• Microphone connector : 8-pin modular (600 Ω)

M RECEIVER

• Receive system : Double-conversion superheterodyne

• Intermediate frequency : VHF 1st IF 15.65 MHz 2nd IF 450 kHz UHF 1st IF 46.05 MHz 2nd IF 450 kHz

• Sensitivity

(at 12 dB SINAD) : Less than 0.18 µV

• Squelch sensitivity

(threshold) : Less than 0.13 µV

• Selectivity

(wide/narrow) : More than 12/6* kHz at –6 dB

Less than 28/18* kHz at –60 dB

*[EUR] and [ITA] versions only

• Spurious and image rejection : More than 60 dB

• Intermodulation rejection ratio : More than 60 dB

• Audio output power

(at 13.8 V) : More than 2.4 W at 10% distortion with an 8Ω load

• External SP1 connector : 2-conductor 3.5(d) mm (

⁄8")/8 Ω

• External SP2 connector : 3-conductor 3.5(d) mm (

⁄8")/8 Ω

1 - 1

SECTION 1 SPECIFICATIONS

144 MHz band 440 MHz band

144.000 – 146.000 430.000 – 440.000

Rx: 136.000 – 174.000*

Rx: 400.000 – 530.000*

Tx: 144.000 – 148.000*1Tx: 430.000 – 440.000*

Rx: 118.000 – 174.000*

430.000 – 450.000*

Tx: 144.000 – 148.000*

Rx: 136.000 – 174.000*

430.000 – 440.000

Tx: 144.000 – 148.000*

Rx: 118.000 – 174.000*1Rx: 400.000 – 530.000*

Tx: 144.000 – 148.000*1Tx: 430.000 – 440.000*

All stated specifications are subject to change without notice or obligation.

Version

EUR

ITA

USA

SEA

CSA

2 - 1

SECTION 2 INSIDE VIEWS

• CONTROL UNIT

• MAIN UNIT

* : Located underside of this point

Q15

Q19 Q20

Q14

V-VCO circuit

Main CPU (IC19: HD6433876N)

EEPROM* (IC17: X25320SI)

PLL IC* IC2 M64076AGP

U-VCO circuit

UHF FM IF IC* (IC8: TA31136FN)

MIC amplifier* (Q88: 2SC4081)

PLL reference oscillator (X1: CR-549 15.2 MHz)

UHF antenna switch (D27*, D37, D39, D72)

UHF 1st mixer (Q42, Q43, D32)

VHF antenna switching (D9*, D16, D18)

VHF power module* (IC1: M67746)

VHF APC DET* (D7, D8: RB706F)

VHF RF amplifier (Q16: 3SK166)

High/Low control IC (IC5: TA75S01F)

VHF 1st mixer (Q15: 3SK166)

AF amplifier (IC12: LA4445)

VHF FM IF IC* (IC28: TA31136FN)

UHF power module* (IC4: SC-1318)

UHF APC DET* (D25, D26: RB706F)

SUB CPU (IC10: HD6433032SK)

T-data buffer amplifier* (Q12: 2SC4081)

R-data buffer amplifier* (Q13: 2SA1576)

CPU reset IC* (IC11: S-80945ANMP-DD9)

LCD controller (IC8: SED1354F0A)

CFL drive (Q14, Q15, Q19*, Q20*)

3 - 1

SECTION 3 DISASSEMBLY INSTRUCTIONS

• Removing the MAIN unit

q Unscrew 1 screw, A, and remove the cover. w Unplug J4 to separate the fan motor from the MAIN unit. e Remove 2 main shield,

B, and TR-A clip,

in the direc-

tion of the arrow.

• Removing the CONTROL unit

q Unscrew 4 screws, A, and remove the cover. w Unplug J5 to separate the speaker and front panel. e Remove rear panel in the deirection of the arrow.

r Remove 6 knobs,

t Unscrew 5 screws,

, and remove the CONTROL unit in

the direction of the arrow.

y Unscrew 2 screws,

, when remove the LCD.

r Unsolder 3 points,

, and unscrew 11 nut, E.

t Remove the MAIN unit in the direction of the arrow.

Cover

MAIN UNIT

Chassis

Rear panel

Front panel

CONTROL UNIT

LCD

4 - 1

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-1-1 DUPLEXER CIRCUIT

The transceiver has a duplexer (low-pass and high-pass filters) on the first stage from the antenna connector to separate the signals into VHF and UHF signals. The low-pass filter (L15, L16, L78, C70–C72) is for VHF signals and the highpass filter (L44, L45, L82, C189, C190, C493) is for UHF signals. The separated signals are applied to each RF circuit.

4-1-2 VHF ANTENNA SWITCHING CIRCUIT

The antenna switching circuit functions as a low-pass filter while receiving. However, its impedance becomes very high while transmitting by turning ON diode (D18). Thus transmit signals are blocked from entering the receiver circuits. The antenna switching circuit employs a 1/4λ type diode switching system. The passed signals are then applied to the VHF RF amplifier circuit.

4-1-3 VHF SQUELCH ATTENUATOR CIRCUIT

The attenuator circuit attenuates the signal strength to a maximum of 10 dB to protect the RF amplifier from distortion when excessively strong signals are received.

The current flow of the antenna switching circuit (D18) is controlled by the [SQL] control via Q33. When the [SQL] control is rotated clockwise deeper than 12 o’clock, the current of D18 is increased. In this case, D18 acts as an attenuator.

4-1-4 VHF RF CIRCUIT

The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.

The signals from the antenna switching circuit pass through the tunable bandpass filter (D15, L25, L26, C1 15–C117). The filtered signals are amplified at the VHF RF amplifier (Q16) and are then enter another 3-stage tunable bandpass filter (D11–D14, L20–L21, C94, C96–C105) to suppress unwanted signals. and improve the selectivity. The filtered signals are applied to the VHF 1st mixer circuit (Q15).

The tunable bandpass filters (D11–D13, D15) employ varactor diodes to tune the center frequency of the RF passband for wide bandwidth receiving and good image response rejection. The PLL lock voltage is used for control voltage of these varactor diodes. The PLL lock voltage is amplified at the DC-amplifier (Q18) and then applied to the CPU (IC19, pin 99). The CPU outputs the control signal to the varactor diodes via the D/A converter (IC3).

4-1-5 VHF 1ST MIXER CIRCUIT

The 1st mixer circuit converts the received signal to a fixed frequency of the 1st IF signal with a 1st LO (V-VCO output) frequency.

The signals from the VHF RF circuit are mixed with the 1st LO signal at the 1st mixer circuit (Q15) to produce a 15.65 MHz 1st IF signal.

4-1-6 VHF 1ST IF CIRCUIT

By changing the PLL frequency, only the desired frequency will pass through a pair of crystal filters at the next stage of the mixer.

The 1st IF signal from the VHF 1st mixer circuit is applied to a pair of crystal filters (FI1) to suppress out-of-band signals via a matching circuit (R61, C88). The filtered signal is amplified at the IF amplifier (Q40) and is then applied to the VHF 2nd mixer circuit (IC28).

4-1-7 VHF 2ND IF AND DEMODULATOR CIRCUITS

The 2nd mixer circuit converts the 1st IF signal to a 2nd IF signal. A double superheterodyne system (which converts receive signals twice) improves the image rejection ratio and obtains stable receiver gain.

The FM IF IC (IC28) contains the 2nd local oscillator, 2nd mixer, limiter amplifier, quadrature detector, and noise detector circuits, etc.

• VHF 2nd IF AND DEMODULATOR CIRCUITS

Mixer

Limiter amp.

2nd IF filter 450 kHz

PLL IC

IC2

15.2 MHz

(15.2 MHz)

RSSI

IC28 TA31136F

1st IF (15.65 MHz) from Q40

"VSQL" signal to the CPU pin 97

11109

875 3

AF signal

VR8V

Squelch level adjustment R196

Active filter

FI4

(FI5)

Noise

detector

4 - 2

The 1st IF signal from the 2nd IF amplifier is applied to the 2nd mixer section of IC28 (pin 16), and is mixed with a 15.2 MHz 2nd LO signal generated by the reference oscillator circuit (X1, IC2) to produce a 450 kHz VHF 2nd IF signal.

The 2nd IF signal from the 2nd mixer passes through the 2nd IF filter (FI4) (during wide channel spacing selection, or passes through FI5 during narrow channel spacing selection; [EUR], [ITA] versions only), where unwanted signals are suppressed. It is then amplified at the limiter amplifier section (IC28, pin 5) and applied to the FM detector section (X2, IC28, pins 10, 11) for demodulation the 2nd IF signal into AF signals.

The FM detector circuit employs a quadrature detection method (liner phase detection), which uses a ceramic discriminator (X2) for phase delay to obtain a non-adjusting circuit. The detected signal from IC28 (pin 9) is applied to the AF circuit.

4-1-8 VHF AF AMPLIFIER CIRCUIT

The AF amplifier circuit amplifies the detected signals to drive a speaker. The AF circuit includes an AF mute circuit for the squelch.

AF signals from FM IF IC (IC28, pin 9) pass through the AF selector (IC21, pins 9, 8), and are then applied to the lowpass (Q83, R370–R373, C406–C409) and high-pass (Q84, R375–R379, C415–C418) filters. The filtered signals are level adjusted at the volume control IC (IC10), and are amplified at the AF power amplifier (IC12, pin 2) passing through the V-AF mute switch (Q70).

The output signal from IC12 (pin 11) drives the external or internal speaker.

4-1-9 VHF SQUELCH CIRCUIT

• NOISE SQUELCH

A noise squelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch.

Some of the noise components in the AF signals from the FM IF IC (IC28, pin 9) are passed through the active filter section (IC28, pin 8, 7), and then applied to the noise detector section (IC28). The variable resister (R196) adjusts the input level of the active filter, and the level is used for squelch threshold reference. The detected noise signals are applied to the CPU (IC19 pin 97) via the “VSQL” line.

The [SQL] (CONTROL unit; R154) controls the input level of the sub-CPU (CONTROL unit; IC10, pin 59) in DC voltage. The sub-CPU reads the angle of the [SQL] rotation, then send the squelch data to the CPU incorporated in the RDATA line. Then the CPU controls V-AF mute switch (Q70) via the “VAMUTE” line.

Even when the squelch is closed, the V-AF mute switch (Q70) opens at the moment of emitting beep tone.

• TONE SQUELCH

The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (CTCSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open.

A portion of the AF signals from the FM IF IC (IC28, pin 9) passes through the active filter (IC20) to remove AF (voice) signals via the AF selector (IC29, pins 5, 4), and is then applied to the CTCSS decoder inside the CPU (IC19, pin 1) via the “TONEIN” line to control the AF mute switch.

Q83, Q84

Q85, Q86

IC8

IC28

VDET

UDET

VAF

UAF

Common

MUTE

UMUTE

IC21

211

• AF amplifier circuit

VHF FM Detector

UHF FM Detector

VDMUTE

UAMUTE

VAMUTE

UDMUTE

VMUTE

AF power

Amplifier

Volume

controller

AF selector

IC10 IC12

Q70

IC11, Q69

Q71

BPF

4 - 3

4-1-10 UHF RF CIRCUIT

The UHF RF signals are passed through part of a duplexer (high-pass filter; L44, L45, L82, C189, C190, C493). The signals are then passed through the low-pass filter (L42, L43, C187, C463), antenna switching circuit (D37, D39, D72), and then amplified at the RF amplifier (Q44). A bandpass filter (FI3) is used at the next stage of the RF amplifier. The RF switch (D35, D33) turns on the UHF RF circuit when UHF signals are received.

4-1-11 UHF 1ST MIXER AND 1ST IF CIRCUITS

The filtered signals from the bandpass filter (FI3) are applied to the 1st mixer circuit (Q43). The applied signals are mixed with a 1st LO signal which comes from the U-VCO circuit (Q20, Q21) to produce a 46.05 MHz 1st IF signal.

The 1st IF signal passes through the 1st IF filter (FI2) to suppress out-of-band signals via a matching circuit (R149, C226). The filtered signal is amplified at the 1st IF amplifier (Q41) and is then applied to the 2nd mixer circuit (IC8).

4-1-12 UHF 2ND IF AND DEMODULATOR CIRCUITS

The 1st IF signal from the IF amplifier is applied to the 2nd mixer section of the FM IF IC (IC8, pin 16). The signal is mixed for producing a 450 kHz 2nd IF signal with a 45.6 MHz 2nd LO signal whitch generated by the tripler circuit (L68, L69, C208–C212) using the PLL reference frequency.

The 2nd IF signal from IC8 (pin 3) is passed through the 2nd IF filter (FI6), and is then applied to the limiter amplifier section in IC8 (pin 5). The signal is applied to the FM detector section in IC8 to demodulate into AF signals.

4-1-13 UHF AF AMPLIFIER CIRCUIT

AF signals from IC8 (pin 9) pass through the AF selector (IC21, pins 3, 4), low-pass filter (Q85, R381–R384, C415–C418) and high-pass filter (Q86, R386–R390, C419–C421).

The filtered signals pass through the volume control IC (IC10). And the level adjusted signals are applied to the AF power amplifier (IC12, pin 5) via the U-AF mute switch (Q71).

The output signal from IC12 (pin 7) drives the external speaker (connected at J2), or it is fed back to the input line of the AF power amplifier (IC12, pin 2: VHF AF line).

4-1-14 UHF SQUELCH CIRCUIT

A portion of the AF signals from the FM IF IC (IC8, pin 9) are applied to the active filter section (IC8, pin 8, 7). The active filter section amplifies and filters noise components. The filered signals are applied to the noise detector section. The variable resister (R229) adjusts the input level of the active filter, and the level is used for squelch threshold reference. The detected noise signals are output from pin 14 as the “USQL” signal, and are then applied to the CPU (IC19, pin

95). The [SQL] (CONTROL unit; R148) controls the input level of

the sub-CPU (CONTROL unit; IC10, pin 61) in DC voltage. The sub-CPU reads the angle of the [SQL] rotation, then send the squelch data to the CPU incorporated in the RDATA line. Then the CPU controls U-AF mute switch (Q71) via the “UAMUTE” line.

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHONE AMPLIFIER CIRCUIT

The microphone amplifier circuit amplifies audio signals from the microphone to a level needed at the modulation circuit. The microphone amplifier circuit is commonly used for both the VHF and UHF bands.

The AF signals from the microphone pass through the MIC sensitivity control circuit (IC25, D66) and MIC mute switch (IC26), and are then amplified at the microphone amplifier (Q88). The amplified signals are applied to the IDC limiter amplifier (IC23b, pin 6). The output signals from the IDC limiter amplifier (IC23b, pin 7) are passed through the splatter filter (IC23a, pin 3, 1) and then applied to each VCO circuit via the deviation adjustment pot.

4-2-2 VHF MODULATION CIRCUIT

The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signals.

The audio signals (MOD) from the splatter filter (IC23a) change the reactance of D3 to modulate the oscillated signal at the V-VCO circuit (Q4, Q5) after passing through the frequency deviation control (R2). The modulated signals are amplified at the buffer amplifiers (Q6, Q7), and are then applied to the drive amplifier circuit via the T/R switching circuit (D4).

4-2-3 VHF DRIVE AMPLIFIER CIRCUIT

The drive amplifier circuit amplifies the VCO oscillating signal to a level needed at the power amplifier.

The RF signals from the buffer amplifier (Q7) pass through the low-pass filter (L5, C35, C36), T/R switch (D4) and attenuator (R33–R35). The Tx signal from the attenuator is amplified at the pre-drive (Q11) and drive (Q12, D5, D6) amplifiers to obtain an approximate 400 mW signal level. The amplified signal is then applied to the RF power amplifier (IC1).

4-2-4 VHF POWER AMPLIFIER CIRCUIT

The power amplifier circuit amplifies the driver signal to an output power level.

IC1 is a power module which has amplification output capabilities of about 70 W. The RF signal from the drive amplifier (Q12) is applied to IC1 (pin 1).

The amplified signals from the power amplifier (IC1, pin 4) pass through the APC detector (D7, D8), antenna switching circuit (D9) and low-pass filter (L15, L16, L78, C70–C72), and is then applied to the antenna connector.

Collector voltage for the driver (Q12) and control voltage for the power amplifier (IC1, pin 2) are controlled by the APC circuit to protect the power module from a mismatched condition as well as to stabilize the output power.

4 - 4

4-2-5 VHF APC CIRCUIT

The APC circuit protects the power amplifier from a mismatched output load and stabilizes transmit output power.

The APC detector circuit (L12, D7, D8) detects forward signals and refrection signals at D7 and D8 respectively. The combined voltage is at a minimum level when the antenna impedance is matched at 50 Ω and is increased when it is mismatched.

The detected voltage is applied to the APC amplifier (IC5, pin

3) and compared with a reference voltage which is supplied from the CPU (IC19, pin 68–pin 75) as a D/A control signal.

When antenna impedance is mismatched, the detected voltage exceeds the reference voltage. The output voltage of the APC amplifier (IC5, pin 4) controls the bias voltage of the power module (IC1) and drive amplifeir (Q12) to reduce the output power via the APC controller (Q30, Q31).

4-2-6 UHF MODULATION CIRCUIT

Audio signals from the splatter filter (IC23a) pass through the frequency deviation control (R78), and are then applied to the modulation circuit (D20) to change the reactance of D20 and modulate the oscillated signal at the U-VCO circuit (Q20, Q21). The VCO output is amplified at the buffer amplifiers (Q22, Q24), and is then applied to the T/R switching circuit (D23) via the low-pass filter (L33, C153, C154).

4-2-7 UHF DRIVE AMPLIFIER CIRCUIT

The VCO signals from the T/R switch (D23) are amplified at the buffer-amplifier (Q27), pre-drive amplifier (Q28) and drive (Q29, D24) amplifier to obtain an approximate 400 mW signal level. The amplified signal is then applied to the RF power amplifier (IC4).

4-2-8 UHF POWER AMPLIFIER CIRCUIT

IC4 is a power module which has amplification output capabilities of about 50 W.

The RF signal from the drive amplifier (Q29) is applied to IC4 (pin 5). The amplified signal from the power amplifier (IC4, pin 1) is passed through the antenna switching circuit (D27) and is then applied to the antenna connector via a bandpass filter (L42–L45, L82, C186–C190, C467, C493).

4-2-9 UHF APC CIRCUIT

The APC detector circuit (D25 and D26) detects forward signals and refrection signals respectively. The combined voltage is at a minimum level when the antenna is matched at 50 Ω and increases when it is mismatched.

The combined voltage is applied to the APC amplifier (IC5, pin 3), and the power setting voltage from the CPU (IC19, pin 68–pin 75) as a D/Acontrol signal is applied to the other input (IC5, pin 1) for the reference.

The output voltage from IC5 (pin 4) is applied to the APC control circuit (Q30, Q31) to control the bias voltage of the P A module (IC4) and drive amplifier (Q29).

4-3 PLL CIRCUITS

4-3-1 GENERAL

A PLL circuit provides stable oscillation of the transmit frequency and the receive local frequency . The PLLcircuit compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by a crystal oscillator and the divided ratio of the programmable divider. IC2 is a dual PLLIC which controls both VCO circuits for VHF and UHF.

4-3-2 VHF LOOP

The generated signal at the V-VCO (Q4, Q5, D3) enters the PLL IC (IC2, pin 6) via buffer-amplifiers (Q6, Q8) and is divided at the programmable divider section and is then applied to the phase detector section.

The phase detector compares the input signal with a reference frequency, and then outputs the out-of-phase signal (pulse-type signal) from pin 8.

The pulse-type signal is converted into DC voltage (lock voltage) at the loop filter (Q99, Q100, R531, C476–C478), and then applied to the V-VCO to stabilize the oscillated frequency.

• VHF APC circuit

L12

VTX

APC

Q30

APC control

Q32

Q31

Power module

Drive

APC amplifier

to antenna

antenna switch

APC detector

POWC

Q12Q11 IC1

IC5

Pre-drive

RF signal from PLL circuit

4 - 5

4-3-3 UHF LOOP

The generated signal at the U-VCO (Q20, Q21, D20, D21) enters the PLL IC (IC2, pin 15) via buffer-amplifiers (Q22, Q23) and is divided at the programmable divider section and is then applied to the phase detector section.

The phase detector compares the input signal with a reference frequency, and then outputs the out-of-phase signal (pulse-type signal) from pin 13.

The pulse-type signal is converted into DC voltage (lock voltage) at the loop filter (Q101, Q102, R538, C481, C483), and then applied to the U-VCO to stabilize the oscillated frequency.

4-4 POWER SUPPLY CIRCUITS

• VOLTAGE LINE

Description

The 13.8V external DC power from the power connector.

The same voltage as the HV line which is controlled by the power switching circuit (Q74, Q75). When the [POWER] switch is pushed, the CPU outputs the “PCTRL” control signal to the power switching circuit to turn the circuit ON.

Common 5 V for the CPU converted from the HV line by the C5V regulator circuit (IC15). The circuit outputs the voltage regardless of the power ON/OFF condition.

Common 5 V produced from the C5V at the PLL5V regulator circuit (Q13, Q14) using control signal from 8V line.

Common 8 V converted from the 13.8V line by the 8V regulator circuit (IC14).

VHF transmit 8 V converted from the 8V line at the VT8V regulator circuit (Q9, Q10).

UHF transmit 8V converted from the 8V line at the UT8V regulator circuit (Q25, Q26).

Receive VR8V produced from the 8V line at the V-BIAS selector (Q34, Q35).

Receive 4R8V produced from the 8V line at the U-BIAS selector (Q34, Q36).

Receive UR8V produced from the 4R8V line at the UR8V switching circuit (D28, D29).

Line

13.8V

C5V

PLL5V

VT8V

UT8V

VR8V

4R8V

UR8V

to the FM IF IC (IC28)

to VHF transmitter circuit

to VHF 1st mixer circuit

• PLL circuit

Loop

filter

Loop

filter

Buffer

Q101, Q102

Q99, Q100

Buffer

Q4, Q5, D3

BPF

to the FM IF IC (IC8)

to UHF transmitter circuit

to UHF 1st mixer circuit

D23

D22

V-VCO

U-VCO

15.2 MHz

45.6 MHz

Shift register/

data latch

PLL IC (IC2)

Prescaler

Phase detector

Programmable counter

Prescaler

Phase detector

Programmable counter

Programmable divider

Buffer

Q22

Buffer

Q24

Buffer

Q23

Q20, Q21 D20, D21

2 DATA 3 CK 4 PLSTB

Tripler

4-5 PORT ALLOCATIONS

4-5-1 CPU (MAIN UNIT; IC19)

4-5-2 SUB-CPU (CONTROL UNIT; IC10)

Outputs reset signal for the LCD controller (IC8).

Input port for serial signal from the main-CPU (MAIN unit; IC19)

Output port for serial signal to the main-CPU (MAIN unit; IC19)

Squelch/volume setting level input ports for VHF band.

Squelch/volume setting level input ports for UHF band.

Input ports for the up/down signals from the VHF main dial.

Outputs brightness control signal for the display backlight.

Outputs control signal for the contrast of display.

59, 60

61, 62

73, 74

75, 76

LRES

TXD

RXD

VSQLV,

VVOLV

USQLV,

UVOLV

VDLA,

VDLB

VDLA,

VDLB

BRITV

CONTV

4 - 6

Input port for the decoded CTCSS signals.

Input ports for the CPU system clock oscillator (X4: 10.000 MHz).

Input port for the reset signal. I/O port for the cloning signal. Outputs strobe signals for the PLL IC

(IC2). Outputs strobe signals for the D/Acon-

vertor (IC3). Outputs serial clock signal for the PLL

IC (IC2) and D/A convertor (IC3). Outputs serial data signals for the PLL

IC (IC2) and D/A convertor (IC3). Input port for serial signal from the

sub-CPU (CONTROL unit; IC10) Output port for serial signal to the sub-

CPU (CONTROL unit; IC10) Outputs clock signal for the EEPROM

IC (IC17). Input port for serial signal from the

EEPROM IC (IC17). Outputs data signal for the EEPROM

IC (IC17). Outputs chip select signal for the EEP-

ROM IC (IC17). Input port for microphone serial signal

via the MDATA controller (IC24). Input port to detect remote microphon

connection.

Low : HM-90/98 is connected. Outputs 1750 Hz Europe tone signal. Outputs power switching circuit (Q74,

Q75) control signal.

High : While turning power ON. Outputs serial clock signal for the elec-

tronic volume IC (IC10). Outputs data signal for the electronic

volume IC (IC10). Input port for packet PTT signal.

High : Packet PTT switch is ON. Input port for the PTT switch.

High : While PTT switch is pushed. PLL unlock signal input port for VHF

band.

High : PLL unlock on VHF band. PLL unlock signal input port for UHF

band.

High : PLL unlock on UHF band. Outputs control signal for the V-BIAS

selector (Q34, Q35).

High : While receiving on VHF band. Output control signal for the U-BIAS

selector (Q34, Q36).

High : While receiving on UHF band. Outputs Rx/Tx pass-bandwidth control

signal.

High : While narrow bandwidth is

selected. ([EUR], [ITA] only)

7, 8

TONEIN

OSC1,

OSC2

RES

CLONEC

PLSTB

STB

DATA

RXD

TXD

ESCK

ESI

ESO

ECS

MICIN

EXTMIC

ETONE

PCTRL

VCK

VDATA

PTTP1

PTTM1

VUNLK

UUNLK

1RX

4RX

W/N

Pin Port

Description

number name

Outputs transmit signal for VHF band.

High : While transmitting on VHF

band.

Outputs transmit signal for UHF band.

High : While transmitting on UHF

band.

Outputs MIC mute control signal.

Low : While DTMF signals are out-

put, etc.

Output ports for output power control signal.

Outputs cooling fan control signal.

High : While transmitting or after

transmission for 2 minute.

Outputs mute control signal for UHF AF signals.

High : While UHF squelch is activate.

Outputs mute control signal for VHF AF signals.

High : While VHF squelch is activate.

Outputs mute control signal for UHF demodulated signals.

High : While UHF demodulated sig-

nals are muted.

Outputs mute control signal for VHF demodulated signals.

High : While VHF demodulated sig-

nals are muted.

Input port for detection signal from the DTMF unit.

Low : While DTMF unit is connected.

Input ports for the decoded DTMF signal from the DTMF unit.

Outputs CTCSS signals. Outputs DTMF signals.

68–75

85–85

90 91

VTX

UTX

MMUTE

POWC0–

POWC7

FUNK

UAMUTE

VAMUTE

UDMUTE

VDMUTE

OPD

Q1–Q4

CTCSS

DTMF

Pin Port

Description

number name

Pin Port

Description

number name

5 - 1

SECTION 5 ADJUSTMENT PROCEDURES

5-1 PREPARATION

All adjustments in this section must be performed on wide bandwidth condition unless specified otherwise. (Narrow bandwidth is selectable for Europe and Italy vertions only.)

‘‘

REQUIRED TEST EQUIPMENT

‘‘

CONNECTION

EQUIPMENT

DC power supply

RF power meter (terminated type)

Frequency counter

FM deviation meter

DC voltmeter

GRADE AND RANGE

Output voltage : 13.8 V DC Current capacity : 20 Aor more

Measuring range : 1–80 W Frequency range : 100–600 MHz Impedance : 50 Ω SWR : Less than 1.2 : 1

Frequency range : 0.1–600 MHz Frequency accuracy: ±1 ppm or better Sensitivity : 100 mV or better

Frequency range : 30–600 MHz Measuring range : 0 to ±10 kHz

Input impedance : 50 kΩ/V DC or better

EQUIPMENT

Audio generator

Standard signal generator (SSG)

Oscilloscope

AC millivoltmeter

External speaker

Attenuator

GRADE AND RANGE

Frequency range : 300–3000 Hz Measuring range : 1–500 mV

Frequency range : 0.1–600 MHz Output level : 0.1 µV–32 mV

(–127 to –17 dBm)

Frequency range : DC–20 MHz Measuring range : 0.01–20 V

Measuring range : 10 mV–10 V Input impedance : 8 Ω

Capacity : 4 W or more Power attenuation : 50 or 60 dB

Capacity : 100 W or more

pin 6 (MIC)

pin 4 (PTT)

pin 7 (GND)

pin 5 (MICE)

to the antenna connector

to the microphone connector

STANDARD SIGNAL GENERATOR

0.1–600 MHz

–127 to –17 dBm (0.1 µV to 32 mV)

RF POWER METER

50 Ω, 1–80 W

AUDIO GENERATOR

300 Hz to 3 kHz

FM DEVIATION

METER

ATTENUATOR

50 dB or 60 dB

POWER SUPPLY

13.8 V, 20 A or more

CAUTION!

DO NOT transmit

while an SSG is connected to the antenna connector.

Controller unit

5 - 2

5-2 PLL AND TRANSMITTER ADJUSTMENTS

PLL LOCK VOLTAGE

PLL REFERENCE FREQUENCY

UHF OUTPUT POWER

VHF OUTPUT POWER

FREQUENCY DEVIATION

ADJUSTMENT

ADJUSTMENT ADJUSTMENT CONDITION

MEASUREMENT

VALUE

POINT

UNIT LOCATION UNIT ADJUST

• VHF displayed freq. :

145.000 MHz

• Receiving

• UHF displayed freq. :

450.000 MHz [USA]

440.000 MHz other

• Output power : Low

• Transmitting

• UHF displayed freq. :

445.000 MHz [USA]

435.000 MHz other

• Output power : High

• Transmitting

• Output power : Low

• Transmitting

• Output power : Mid-L

• Transmitting

• Output power : Mid-H

• Transmitting

• VHF displayed freq. :

145.000 MHz [EUR]

146.000 MHz other

• Output power : High

• Transmitting

• Output power : Low

• Transmitting

• Output power : Mid-L

• Transmitting

• Output power : Mid-H

• Transmitting

• UHF displayed freq. :

445.000 MHz [USA]

435.000 MHz other

• Output power : Low

• Connect an audio generator to the [MIC] connector and set as:

1 kHz/ 80 mV [USA] 1 kHz/ 20 mV other

• TONE : OFF

• Set an FM deviation meter as:

HPF : 50 Hz LPF : 20 kHz De-emphasis : OFF Detector : (P–P)/2

• Transmitting

• VHF displayed freq. :

145.000 MHz [EUR]

146.000 MHz other

• Output power : Low

• Transmitting

• IF bandwidth : Narrow

[EUR, ITA] only

• Transmitting

MAIN

Rear

panel

Rear

panel

Rear

panel

Rear

panel

Connect a digital multi-meter or oscilloscope to the check point CP-LV.

Loosely couple the frequency counter to the antenna connector.

Connect an RF power meter to the antenna connector.

Connect an FM deviation meter to the antenna connector through an attenuator.

1.65 V

450.0000 MHz [USA]

440.0000 MHz other

35 W

2–7 W

8–15 W

16–24 W

50 W

2–7 W

8–15 W

16–24 W

±4.8 kHz

±2.0–±2.8 kHz

MAIN

C84

R121

Verify

R119

Verify

R78

Verify

5 - 3

DC power supply

13.8 V / 20 A

R119

UHF output power adjustment

CP-LV

PLL lock voltage check point

PLL lock voltage adjustment

VHF deviation adjustment

R119

VHF output power adjustment

C84

Reference frequency adjustment

R78

UHF deviation adjustment

Controller

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