Icom IC-2200H User Manual
VHF TRANSCEIVER
i2200H
SERVICE
MANUAL
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RadioAmateur.EU
MODEL VERSION SYMBOL
EUR
TPE
KOR
EXP
EXP-1
INTRODUCTION
This service manual describes the latest service information
for the IC-2200H VHF TRANSCEIVER at the time of publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOTreverse the polarities of the power supply when con-
necting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the transceiver’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component par t number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1130008350 S.IC LV2105V IC-2200H MAIN UNIT 5 pieces
8810009610 Screw
FH M2.6×6 ZK
IC-2200H Cover 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the
transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insu-
lated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the trans-
ceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7.
ALWAYS connect a 40 dB to 50 dB attenuator between
the transceiver and a deviation meter or spectrum analyzer when using such test equipment.
8.
READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
To upgrade quality, any electrical or mechanical par ts and
internal circuits are subject to change without notice or
obligation.
Europe
EUR-1
USA
Taiwan
U.S.A.
Korea
Export
Europe-1
Export-1
IC-2200H
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
2 - 1 IC-2200H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 - 1
2 - 2 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 - 2
SECTION 3 OPTIONAL UNIT INSTALLATION
SECTION 4 CIRCUIT DESCRIPTION
SECTION 5 ADJUSTMENT PROCEDURES
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISSASEMBLY
7 - 1 IC-2200H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 - 1
7 - 2 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 - 1
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 - 1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 1
9 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 3 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
9 - 4 HM-118TN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 7
SECTION 10 BLOCK DIAGRAMS
10 - 1 IC-2200H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 - 1
10 - 2 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 - 2
SECTION 11 VOLTAGE DIAGRAMS
11 - 1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 1
11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 2
11 - 3 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 3
SECTION 12 HM-118/N (OPTIONAL UNIT)
12 - 1 INSIDE VIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 - 1
12 - 2 BOARD LAYOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 - 1
12 - 3 MECHANICAL PARTS LIST AND DISSASEMBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 - 2
SECTION 13 UT-108 (OPTIONAL UNIT)
13 - 1 BOARD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 - 1
SECTION 14 UT-115 (OPTIONAL UNIT)
14 - 1 BOARD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 - 1
14 - 2 SEMI-CONDUCTOR INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 - 2
14 - 3 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 - 2
14 - 4 VOLTAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 - 3
1 - 1
SECTION 1 SPECIFICATIONS
M GENERAL
• Frequency range :
*1Specifications guaranteed 144.000 – 146.000 MHz only
*
2
Specifications guaranteed 144.000 – 148.000 MHz only
• Mode : FM, AM (Receive only)
• Number of memory channel : 206 (include in 6 band edges memory and 1 call channel)
• Usable temperature range : –10˚C to +60˚C; +14˚F to +140˚F
• Scan type : Full, Program, Priority, Memory channel, Bank, Skip and Tone scans
• Frequency resolution : 5, 10, 12.5, 15, 20, 25, 30 and 50 kHz
• Frequency stability : ±10 ppm (–10˚C to +60˚C; +14˚F to +140˚F)
• Power supply requirement : 13.8 V DC ±15 % (negative ground)
• Current drain (at 13.8 V DC) : Receive Standby (squelched) 0.8 A
Max. audio 1.0 A
Transmit at 65 W or 50 W 15.0 A (except [TPE])
at 25 W 9.0 A
at 24 W 10.0 A ([TPE] only)
at 10 W 6 A (except [TPE])
at 5 W 5 A
• Antenna connector : SO-239 (50 Ω)
• Dimensions : 140(W)×40(H)×146(D) mm;
(projections not included) 5
1
⁄2(W)×19⁄16(H)×53⁄4(D) inch
• Weight : Approx. 1.25 kg; 2 lb 12 oz
M TRANSMITTER
• Output power :
• Modulation system : Variable reactance frequency
• Maximum frequency deviation : ±5.0/±2.5* kHz *except [EXP-1]
• Spurious emissions : Less than –60 dBc
• Microphone connector : 8-pin modular (600 Ω)
M RECEIVER
• Receive system : Double-conversion superheterodyne
• Intermediate frequency : 1st 21.7 MHz
2nd 450 kHz
• Sensitivity (at 12 dB SINAD) : Less than 0.18 µV
• Squelch sensitivity (threshold) : Less than 0.13 µV
• Selectivity : (Wide) More than ±6 kHz at 6 dB, More than ±14 kHz at 60 dB
(Narrow)* More than ±3 kHz at 6 dB, More than ±9 kHz at 55 dB
*except [EXP-1]
• Spurious and image rejection : More than 60 dB
• Audio output power
(at 13.8 V) : More than 2.4 W at 10% distortion with an 8Ω load
• External speaker connector : 2-conductor 3.5(d) mm (
1
⁄8")/8Ω
All stated specifications are subject to change without notice or obligation.
High Middle-high Middle-low Low
65 W 25 W 10 W 5 W
50 W 25 W 10 W 5 W
24 W 10 W – 5 W
Version
except
[TPE], [KOR
]
[KOR]
[TPE]
Receive (MHz) Transmit (MHz)
118.000 – 174.000*
1
144.000 – 146.000
118.000 – 174.000*
2
144.000 – 148.000
118.000 – 174.000*
2
136.000 – 174.000*
2
144.000 – 146.000 144.000 – 146.000
Version
[EUR]
[USA]
[EXP], [EXP-1]
[EUR-1], [TPE],
[KOR]
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1 - 2
• UT-115 SPECIFICATIONS
M GENERAL
• Usable temperature range : –10˚C to +60˚C; +14˚F to +140˚F
• Power supply requirement : 5.0 V DC
(4.5 V–8.5 V for AMBE IC VCC line)
• AF input level : 1 V
p-p typical
• Modulation output level : 350 mV
p-p typical
• Demodulation input level : 500 mV
p-p typical
• AF output level : 750 mV
p-p typical
• CODEC type : AMBE
• Transfer speed : 4.8 kbps
• Control signal input voltage : 3.0 V–5.0 V for High
0 V for Low
• Control signal output voltage : Open collector for High
0 V for Low
• Current drain (at 5.0 V DC) : 55 mA typical
• Dimentions : 30(W)×38(D) mm;
(projections not included) 1
3
⁄16(W)×11⁄2(D) inch
• Weight : Approx. 6 g;
7
⁄32 oz
(accessoreis not included)
• Connector : AXN430C330
All stated specifications are subject to change without notice or obligation.
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2 - 1
SECTION 2 INSIDE VIEWS
2-1 IC-2200H
• MAIN UNIT (TOP VIEW)
Power module
(IC10: S-AV36)
Discriminator
(X2: CDB450C24)
AGC
(Q38: XP6501)
Reference oscillator
(X1: CR-779 21.25MHz)
Power switch circuit
Q28*: 2SC4684
Q30: DTA143TUA
Q31: DTC143ZU
Speaker
AF power amplifier
(IC9: TA7252AP)
VCO circuit
*Located under side of the point
IF filter
FI1: CFWS450F
FI2: CFWS450HT
Power module
(IC10: S-AV36)
Discriminator
(X2: CDB450C24)
AGC
(Q38: XP6501)
Reference oscillator
(X1: CR-779 21.25MHz)
Power switch circuit
Q28*: 2SC4684
Q30: DTA143TUA
Q31: DTC143ZU
Speaker
AF power amplifier
(IC9: TA7252AP)
VCO circuit
*Located under side of the point
2nd IF filter
FI1: CFWS450F
FI2: CFWS450HT
• MAIN UNIT (BOTTOM VIEW)
APC controller
(IC6: NJM3404AV)
C5V regulator
(IC8: TA78L05F)
+8V regulator
(IC7: TA7808F)
TX/RX switch
(D6, D7: MA77)
PLL IC
(IC1: LV2105V)
Enphasis switch
(Q41: 2SC4617)
RF amplifier
(Q27: 3SK299)
Mixer
(Q19: 3SK299)
IF amplifier
(Q16: 2SC4406)
IF detector
(IC4: TA31136FN)
D/A converter
(IC5: M62363FP)
APC controller
(IC6: NJM3404AV)
C5V regulator
(IC8: TA78L05F)
+8V regulator
(IC7: TA7808F)
TX/RX switch
(D6, D7: MA77)
PLL IC
(IC1: LV2105V)
Enphasis switch
(Q41: 2SC4617)
RF amplifier
(Q27: 3SK299)
1st Mixer
(Q19: 3SK299)
IF amplifier
(Q16: 2SC4406)
FM IF IC
(IC4: TA31136FN)
D/A converter
(IC5: M62363FP)
2-2 HM-133V
2 - 2
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CPU
CPU
(IC1: µPD789071)
(IC1: µPD789071)
LED driver
LED driver
Q6, Q7: 2SA1586
Q6, Q7: 2SA1586
DS10*: LT1EP53A
DS10*: LT1EP53A
5V regulator
5V regulator
Q1: 2SC2712
Q1: 2SC2712
D1: MA8056
D1: MA8056
Regulator switch
Regulator switch
Q8: 2SC2712
Q8: 2SC2712
Q9: DTB113ZK
Q9: DTB113ZK
Reset IC
Reset IC
(IC3: BD5245G)
(IC3: BD5245G)
LED driver
LED driver
Q4, Q5: 2SA1586
Q4, Q5: 2SA1586
DS11*: LT1EP53A
DS11*: LT1EP53A
EE-PROM
EE-PROM
(IC6: BR24L02FV)
IC6: BR24L02FV
[MAIN-A] unit only
Data buffer circuit
Data buffer circuit
Q2: DTC114EU
Q2: DTC114EU
Q3: DTA114EU
Q3: DTA114EU
*Located under side of the point
SECTION 3 OPTIONAL UNIT INSTALLATION
3 - 1
➀ Remove [DIAL] and unscrew the 2 allen-socket bolts from
the front panel using with an allen wrench (2.5 mm;
1
⁄10″).
NOTE: When attaching the front panel to the main unit,
make sure the flat cable are running in the groove to prevent catching between front panel and main unit.
➅ Return the front panel and the allen-socket bolts to their
original position.
➂ Attach the insulation sheet (supplied as accessory) to IC
on the Front unit.
➃ Remove the protective paper attached to the bottom of
the optional unit to expose the adhesive strip.
➁ Detach the front panel from the main unit.
➄ Intall the unit as illustrated below. Insert tightly to avoid
bad contact.
Allen-socket
bolts
Flat cable
Insulation sheet
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
(MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
The circuit does not allow transmit signals to enter receiver
circuits.
Received signals enter the antenna connector and pass
through the low-pass filter (L47, L48, C208, C210, C217).
The filtered signals are passed through the λ/4 type antenna switching circuit (D16, D19, L45, L46) and limiter circuits
(D15). The signals are then applied to the squelch attenuator circuit.
4-1-2 SQUELCH ATTENUATOR CIRCUIT
(MAIN UNIT)
The attenuator circuit attenuates the signal strength to a
maximum of 10 dB to protect the RF amplifier from distortion
when excessively strong signals are received.
The current flow of the antenna switching circuit (D16, D19)
is controlled by the [SQL] control via the attenuator controller (IC6a, D18). When the [SQL] control is rotated clockwise deeper than 12 o’clock, the current of D16 and D19 is
increased. In this case, D16 and D19 act as an attenuator.
4-1-3 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the squelch attenuator circuit pass through
the tunable bandpass filter (D13). The filtered signals are
amplified at the RF amplifier (Q27) and then enter another
three-stage bandpass filters (D9–D11) to suppress unwanted signals. The filtered signals are applied to the 1st mixer
circuit (Q19).
The tunable bandpass filters (D13–D16) employ varactor
diodes to tune the center frequency of the RF passband for
wide bandwidth receiving and good image response rejection. These diodes are controlled by the CPU (LOGIC unit;
IC1) via the D/A convertor (IC5).
4-1-4 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signals to a fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a pair of crystal filters at the next stage of
the 1st mixer.
The RF signals from the bandpass filter are applied to the
1st mixer circuit (Q19). The applied signals are mixed with
the 1st LO signal coming from the RX-VCO circuit (Q7, D5,
D38) to produce a 21.7 MHz 1st IF signal. The 1st IF signal
passes through a pair of crystal filters (FI3, FI4) to suppress
out-of-band signals. The filtered signal is amplified at the 1st
IF amplifier (Q16), and applied to the 2nd IF circuit via the
limiter circuit (D29).
4-1-5 2ND IF AND DEMODULATOR CIRCUITS
(MAIN unit)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double-conversion superheterodyne system
improves the image rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q16) is applied to the
2nd mixer section of the FM IF IC (IC4, pin 16) and is then
mixed with the 2nd LO signal for conversion to a 450 kHz
2nd IF signal.
IC4 contains the 2nd mixer, limiter amplifier, quadrature
detector, S-meter detector, active filter and noise amplifier
circuits, etc. A frequency from the PLL reference oscillator is
used for the 2nd LO signal (21.25 MHz).
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
(for wide)
(for narrow)
X1
21.25 MHz
IC4 TA31136FN
12
1st IF from the
IF amplifier (Q16)
"SD" signal to the CPU
(FRONT unit; IC1, pin 4)
11109
8
Q37, Q38
7
AF signal "DETO"
R5V
X2
2
Active
filter
Noise
detector
FM
detector
13
"NOIS" signal to the CPU
(FRONT unit; IC1, pin 26)
RSSI
Noise
comp.
PLL IC
IC1
116
"SQLIN" signal from
the D/A converter IC
(IC5, pin 11)
AM
detector
IC12
AM/FM
selector
FI2
3
FI1
• 2ND IF AND DEMODULATOR CIRCUIT
4 - 2
The 2nd IF signal from the 2nd mixer (IC4, pin 3) passes
through the ceramic filter (FI1) (during wide channel spacing
selection or passes through FI2 during narrow channel
spacing selection; [W/N] only).
4-1-6 AM/FM SELECTOR CIRCUIT (MAIN UNIT)
IC-2200H can receive AM and FM signal. The 2nd IF signal
is detected AM or FM detector circuits respectively.
(1) AM DETECTOR CIRCUIT
The filtered signal is applied to the AM detector circuit (Q37,
Q38) to demodulate 2nd IF signal into AM AF signals. The
AM AF signals are applied to the AF circuit via the AM/FM
selector switch (IC12, pin 6).
(2) FM DETECTOR CIRCUIT
The filtered signal is amplified at the limiter amplifier section
(IC4, pin 5), and is then applied to the quadrature detector
section (IC4, pins 10, 11 and X2) to demodulate the 2nd IF
signal into FM AF signals. The FM AF signals are output
from pin 9 (IC4) and are then applied to the AF circuit via the
AM/FM selector switch (IC12, pin 7).
4-1-7 AF CIRCUITS (LOGIC UNIT)
The AF circuits are composed of digital and analog AF circuits. The AF signals are amplifies the demodulated AF signals to drive a speaker.
(1) IN CASE OF DIGITAL AF SIGNALS
The digital AF signals are applied to the optional digital unit
(UT-115*) via the J4 (pin 23) by the “DETO” line. The audio
signals that are converted to analog signals at the UT-115
are applied to the analog selector circuit (IC525, pin 8) from
the optional digital voice unit passed through the J4 (pin 22)
via the “AFOUT” line. The signals pass through the highpass filter (IC3c, pins 8, 9) from the analog selector (IC525,
pin 9), and are then applied to the analog switch (IC6, pin 1).
*Refer to “4-6 UT-115 CIRCUIT DESCRIPTION” (page 4-7 )
in detail.
(2) IN CASE OF ANALOG AF SIGNALS
The analog AF signals are applied to the analog selector
(IC525, pin 11), and pass through the high-pass filter (IC3c,
pins 8, 9). The filtered signals are applied to the analog
switch (IC6, pin 1).
The audio signals are applied to the AF mute switch (MAIN
unit; Q29) via the VOL adjust pot (R61). The signals are
amplified at the AF amplifier (MAIN unit; IC9, pin 1) to obtain
2.4 W audio output power after being passed through the
emphasis switch (MAIN unit; Q41). The amplified AF signals
are applied to the speaker via the J4 (MAIN unit) and J6
(MAIN unit).
4-1-8 SQUELCH CIRCUITS
(MAIN AND LOGIC UNITS)
•
NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in the
AF signals, the squelch circuit switches the AF mute switch.
A portion of detected audio signals from the FM IF IC (IC4,
pin 9) are applied to the active filter section of the IC (IC4,
pin 8) as “SQLIN” signal, after passing through the D/A converter (IC5, pin 12). The active filter section of the IC amplifies and filters noise components. The filtered signals are
applied to the noise detector section in the IC and output
from pin 13 as the “NOIS” signal.
The “NOIS” signal from IC4 (pin 13) is applied to the CPU
(LOGIC unit; IC1, pin 26). The CPU analyzes the noise condition and outputs “AFMUTE” and “FILC” signals via the I/O
expander IC (LOGIC unit; IC2) to toggle the AF mute (Q29)
and emphasis (Q41) switches.
Even when the squelch is closed, the AF mute switch (Q29)
opens at the moment of emitting beep tones.
• TONE SQUELCH
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when noise squelch is open.
AF signals from the FM IF IC (IC4, pin 9) are applied to the
AM/FM selector (IC12, pin 6 or 7), and then pass through
the analog selector (LOGIC unit; IC525, pins 10, 11). The
signals pass through the low-pass filter (LOGIC unit; Q3) to
remove AF (voice) signals, and is applied to the CTCSS
decoder inside the CPU (LOGIC unit; IC1, pin 1) via the
“CTCIN” line to control the AF mute switch.
Analog selector
(IC525)
Analog switch
(IC6)
Optional unit
(UT-115)
"DETO" AF signal from the AM/FM
selector (MAIN unit; IC12, pin 1)
11
1
R61
11
IC3
Q29
Q41
8
15
9
9
10
8
AF
IC9
Speaker
(SP1)
HPF
LOGIC unit
MAIN unit
AF
mute
Emphasis
switch
AF
volume
• AF CIRCUIT
4 - 3
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(LOGIC unit)
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.
The AF signals from the microphone pass through the
microphone switch (IC2, D4), and are then amplified at the
microphone amplifier (IC3a ,pin 2). The amplified signals
pass through (or bypass) the ALC circuit.
4-2-2 ALC CIRCUIT (LOGIC UNIT)
The ALC (Automatic Level Control) circuit reduces the gain
of IF amplifiers in order for the transceiver to output a constant RF power set by the RF power setting even when the
supplied voltage shifts, etc.
• IN CASE OF PASSING THROUGH THE ALC CIRCUIT
The amplified signals are applied to the ALC switch (IC520,
pin 3), and are then output from pin 4. The signals are
applied to the ALC amplifier (IC514, pin 3), and are then
reapplied to the ALC switch (IC520, pin 8). The signals pass
through the high-pass filter (IC3d, pins 12, 14), and are then
applied to the analog switch (IC6, pin 4).
• IN CASE OF BYPASSING THE ALC CIRCUIT
The amplified signals are applied to the ALC switch (IC520,
pin 2), and are then output from pin 1. The signals are
applied to the ALC switch (IC520, pin 9) again, and then
pass through the high-pass filter (IC3d, pins 12, 14) via the
IC520, pin 10. The signals are applied to the analog switch
(IC6, pin 4).
4-2-3 DIGITAL SWITCH CIRCUIT (LOGIC UNIT)
The signals from the analog switch (IC6, pin 3) pass through
the high-pass filter (IC3, pins 6, 7), and are then reapplied to
the analog switch (IC6, pin 9). The signals are applied to the
DI/AN switch via the “MOD_I” line.
• IN CASE OF DIGITAL AF SIGNALS
The AF signals are applied to the DI/AN switch (IC522, pin
10), and are then applied to the optional digital voice unit
after being passed through the J4 (pin 4) via the “ANALOGUE_MOD_IN” line. The A/D converted AF signals are
applied to the DI/AN switch (IC522, pin 1) from the J4 (pin 3)
via the “DIGITAL_MOD_OUT” line. The digital AF signals
from DI/AN switch (IC522, pin 2) are applied to the modulation circuit after being passed through the J3 via the
“MODIN” line.
• IN CASE OF ANALOG AF SIGNALS
The AF signals are applied to the DI/AN switch (IC522, pin
9), and are then reapplied to the switch (pin 4) from pin
8.The signals output from the switch (pin 3) as analog AF
signals , and are then applied to the modulation circuit after
being passed through the J3 via the “MODIN” line.
4-2-4 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The digital or analog audio signals (MODIN) change the
reactance of D2 and D4 to modulate the oscillated signal at
the TX-VCO circuit (Q6). The modulated signal is amplified
at the LO amplifier (Q9) and buffer amplifier (Q11), then
applied to the drive amplifiers.
4-2-5 DRIVE AMPLIFIER CIRCUIT (MAIN UNIT)
The drive amplifier circuit amplifies the VCO oscillating signal to the level needed at the power amplifier.
The RF signal from the buffer amplifier (Q11) passes
through the T/R switch (D6) and is amplified at the pre-drive
(Q17) and drive (Q35) amplifiers. The amplified signal is
applied to the power amplifier circuit.
4-2-6 POWER AMPLIFIER CIRCUIT (MAIN UNIT)
The power amplifier circuit amplifies the driver signal to an
output power level.
The RF signal from the drive amplifier (Q35) is applied to the
power module (IC10) to obtain 65 W (50 W for Korea version, 25 W for Taiwan version) of RF power.
The amplified signals is passed through the antenna switching circuit (D12), APC detector circuit (D14, D17, L39), and
low-pass filter (L47, L48, C208, C210, C217) and is then
applied to the antenna connector.
Control voltage for the power amplifier (IC10, pin 2) are controlled by the APC circuit to protect the power module from
a mismatched condition as well as to stabilize the output
power.
Microphone
MIC
switch
"THROUGH" from the CPU
(MAIN unit; IC1, pin 80)
"ALC" from the CPU
(MAIN unit; IC1, pin 81)
"THROUGH" from the CPU
(MAIN unit; IC1, pin 80)
IC3A
IC2, D4
Through
switch
Switch
ALC
switch
ALC
switch
MIC
IC514
IC520 IC520
IC520
Q524
IC525
to the modulator circuit
ALC
Power
supply
• ALC CIRCUIT
4 - 4
4-2-7 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the power amplifier from a mismatched output load and stabilizes the output power.
The APC detector circuit (D14, D17, L39) detects forward
signals and reflection signals at D14 and D17 respectively.
The combined voltage is at minimum level when the antenna impedance is matched at 50 Ω and is increased when it
is mismatched.
The detected voltage is applied to the differential amplifier
(IC6, pin 2), and the power setting voltage is applied to the
other input (pin 1) for the reference.
When antenna impedance is mismatched, the detected voltage exceeds the power setting voltage. The output voltage
of the differential amplifier (IC6, pin 1) controls the input current of the power module (IC10) to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit frequency and the receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.
An oscillated signal from the VCO passes thorough the LO
and buffer amplifiers (Q9, Q12) is applied to the PLL IC (IC1,
pin 6) and is prescaled in the PLL IC based on the divided
ratio (N-data). The reference signal is generated at the reference oscillator (X1) and is also applied to the PLL IC. The
PLL IC detects the out-of-step phase using the reference
frequency and outputs it from pin 15. The output signal is
passed through the loop filter (Q2, R6, R11–R15, C11, C12)
and is then applied to the VCO circuit as the lock voltage via
the “LV” line.
4-3-2 VCO CIRCUIT (MAIN unit)
The VCO circuit contains a separate TX-VCO (Q6, D2, D4)
and RX-VCO (Q7, D5, D38). The oscillated signal is amplified at the LO (Q9) and buffer (Q11) amplifiers, and is then
applied to the T/R switching circuit (D6, D7). Then the Tx
and Rx signals are applied to the pre-driver (Q17) and 1st
mixer (Q19) respectively.
A portion of the signal from Q4 is amplified at the buffer
amplifier (Q6) and is then fed back to the PLL IC (IC1 pin 2)
as the comparison signal.
Power
amp.
IC6
APC
amp.
Driver
amp.
+
—
Pre
drive
HV
to the antenna
T1
TXC
IC11
Q26, Q39, Q40
RF signal
T8
APC control circuit
Q17
Q35
IC10
Power detector circuit
L39
D14 D17
• APC CIRCUIT
Shift register
Prescaler
Phase
detector
Charge
pump
Loop
filter
Programmable
divider
Reference
divider
X1
21.25 MHz
1
LO
Buffer
Buffer
2
3
4
PLLCK
PLLDATA
PLLSTB
to transmitter circuit
to 1st mixer circuit
D6
D7
Q11
Q12
Q9
9
6
Q6, D2, D4
TX VCO
Q7, D5
RX VCO
IC1 LV2105V
21.25 MHz 2nd LO signal
to the FM IF IC (IC4, pin 2)
16
LPF
LPF
• PLL CIRCUIT
Downloaded by
RadioAmateur.EU
4 - 5
4-3-3 REFERENCE OSCILLATOR CONTROL
CIRCUIT (LOGIC AND MAIN UNITS)
The reference oscillator control circuit changes the reference frequency when using digital voice function.
When digital voice signals output from the optional digital
voice unit, the “REFMOD” signal outputs from it via the J4
(pin 4) at the same time. The “REFMOD” signal is applied to
the amplifier (IC521, pin 3), and passes through the CTCSS
switch (IC524, pins 6 and 1). The signal is applied to the D/A
convertor (MAIN unit; IC5, pin 13) via the “CTCSS” line. The
output signal from the D/A convertor (MAIN unit; IC5, pin 14)
is applied to the reference oscillator (MAIN unit; X1) to control the reference frequency while transmitting digital signals
as “DTC” line.
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINES
Description
The 13.8 V voltage from the connected DC
power supply.
The same voltage as the HV line which is controlled by the HVSW circuit (Q28, Q30, Q31).
When the [POWER] switch (LOGIC unit; S1) is
pushed, the CPU (LOGIC unit; IC1, pin 40) outputs the “PWRON” control signal to the power
switching circuit to turn the circuit ON.
Common 5 V for the CPU (LOGIC unit; IC1)
converted from the HV line by the C5V regulator
circuit (IC8). The circuit outputs the voltage
regardless of the power ON/OFF condition.
Common 8 V converted from the SWHV line by
the +8V regulator circuit (IC7).
Common 5 V converted from the +8V line by the
+5V regulator circuit (Q21, Q22).
Transmit 8 V controlled by the T8 regulator circuit (Q14, Q15) using the “TXC” signal from the
I/O expander IC (IC2, pin 6). The voltage is converted from the +8V line at the regulator circuit.
Receive 5 V controlled by the R5 regulator circuit (Q25) using the “RXC” signal from the I/O
expander IC (IC2, pin 5). The voltage is converted from the +5 V line at the regulator circuit.
Line
HV
SWHV
C5V
+8V
+5V
T8
R5V
Pin
number
2
3
10
11
14
15
22
23
Port
name
T3
SQLATT
FC
SQLIN
DTC
MOD
T2
T1
Description
Outputs RF tracking voltage while
receiving.
Outputs attenuator control signal.
Outputs reference frequency control
voltage.
Outputs squelch control signal to
adjust threshold level.
Outputs DTCS slope correction signal.
Outputs transmitting deviation control
signal.
Outputs RF tracking voltage while
receiving.
• Outputs RF tracking voltage while
receiving.
• Outputs transmitting power control
signal while transmitting.
4-5 PORT ALLOCATIONS
4-5-1 D/A CONVERTER IC (MAIN UNIT; IC5)
Pin
number
4
5
6
11
14
Port
name
AFMUTE
RXC
TXC
W/N
SHIFT
Description
Outputs AF mute control signal.
High: While muting.
Outputs R5 regulator (Q25) control
signal.
Low: While receiving.
Outputs T8 regulator (Q14 and Q15)
control signal.
High: While transmitting.
Outputs 2nd IF filter select signal
([W/N] version ONLY).
High: While wide passband width
(±5.0 kHz) is selected (FI1 is
selected).
Low: While narrow passband width
(±2.5 kHz) is selected (FI2 is
selected).
Outputs VCO regualtor (Q1, Q3, Q5,
Q8, D1) control signal.
Low: While transmitting.
High: While receiving.
4-5-2 EXPANDER IC (MAIN UNIT; IC2)
Port
name
IS0–IS2
KS1, KS2
KR3–KR0
PTT
DI_SEC
TX_DIGI
SO
OPSCK
OPV1
DASTB
OPV2
EXTMIC
DUSE
ESCK
ESDA
OP_PS
THROUGH
ALC
OPT3
OPT2
OPT1
SEG1–
SEG36
COM4–
COM1
VL3–
VL1
IDET
4-5-3 CPU (LOGIC UNIT; IC1)
Pin
number
1
2
3
4
5
6
7
8
9
10
14
19
25
26
28
29
30
31
34
35
40
42
43
44
45
46
47
49
51
Port
name
CTCIN
SQLV
MICUD
SD
LVIN
TEMP
DET0
COLOR
DIM0
DIM1
CSHIFT
RESET
PWRSW
NOIS
DICK
DIUD
CLIN
CLOUT
SCK
BUSY
PWRON
BSHIFT
PLLSTB
PLLCK
EXSTB
OPV3
UNLK
REMO
MICS
AFON
Description
Input port for the CTCSS/DTCS signals.
Input port for squelch volume detecting signal.
Input port for the [∫] and [√] switches
from the external microphone.
Input port for the S-meter voltage
detecting signal.
Input port for the PLL lock voltage.
Input port for the transceiver’s internal
temperature detecting signal.
Input port for the weather channel
alert detecting sinal.
Outputs LCD backlight color select
signal.
Low: Umber color is selected.
Output LCD backlight brightness controls signals
Outputs the CPU clock shift control
signal.
Input port for the reset signal.
Input port for [POWER] switch.
Low: [POWER] switch is pushed.
Input port for the noise pulse signal for
squelch and CPU.
Input ports for encoder signals.
Input port for the cloning signal.
Output port for the cloning signal.
Outputs serial clock signal to the D/A
convertor (MAIN unit; IC5, pin 7).
Outputs “BUSY” signal to the UT-115.
Outputs [POWER] switch control signal.
High: [POWER] is ON.
Outputs band shift signal.
Low : While receiving Air band
(118–136 MHz).
Outputs strobe signal to the PLL IC
(MAIN unit; IC1, pin 4).
Outputs clock signal to the PLL IC
(MAIN unit; IC1, pin 2).
• Outputs strobe signal to the
expander IC (MAIN unit; IC2, pin 1).
• Input port for the optional unit detecting signal.
Input port for the PLL unlock signal.
Input port for the HM-133V remote
microphone signals.
Output transmitting/receiving AF filter
select signal to the analog swtich (IC6,
pin 6 [“AFON” is applied to the
pin 12]).
Pin
number
53–55
56, 57
58–61
62
64
65
66
67
68
69
73
74
75
76
77
80
81
84
85
86
90,
92–127
128–131
134–136
144
Description
Output initial matrix strobe signals.
Output key scan signals
Input ports for the keyboard matrix
signals.
Input port for the [PTT] switch signal.
High: While transmitting.
Outputs digital/analog select signal
while the UT-115 is installed.
High : Digital is selected.
Outputs filter characteristic control signal while the UT-115 is installed.
Low : While transmitting digital sig-
nal.
• Outputs serial data to D/A convertor
(MAIN unit; IC5, pin 8).
• Outputs DTMF clock signal to the
expander IC (MAIN unit; IC2, pin 2).
Outputs clock signal to the optional
unit.
• Input port for the optional unit detecting signal.
• Outputs strobe signal to the D/A converter (MAIN unit; IC5, pin 6).
Input port for the optional unit detecting signal.
Input port for detecting signal whether
the multifunction microphone is connected or not.
Low: The multifuntion microphone is
connected.
Outputs low-pass filter cut-off frequency control signal when using DTCS.
Outputs clock signal to the EEPROM
(IC5, pin 6).
I/O port for data signals from/to the
EEPROM (IC5, pin 5).
Outputs the optional unit power supply
controll signal.
High : Power is ON.
Outputs the ALC circuit control signal.
High : The ALC circuit is OFF.
Outputs the ALC circuit control signal.
High : The ALC circuit is ON.
I/O ports for the optional unit control
signals.
Output LCD segment signals.
Output LCD common signals.
Output LCD device signals.
Input port for the current drain detecting signal while transmitting.
4 - 6
4-6 UT-115 CIRCUIT DESCRIPTION
4-6-1 RECEIVER CIRCUIT
The detected digital signals “FMDET” from the connected
transceiver via the J301 (pin 22) are amplified at the buffer
amplifier (IC251, pin 2). The amplified signals are applied to
the GMSK modem circuit (IC252, pin 11), and are then
applied to the CPU (IC204) as clock synchronizer digital signal. The digital signals from the CPU are applied to the
AMBE voice CODEC IC (IC151) to precess code extention,
and are then applied to the linear CODEC IC (IC50) as 32
bits digital voice data. The applied digital signals are converted to the analog AF signals at the D/A converter section
(IC50), and are then applied to the connected transceiver
via the J301 (pin 21) as “DAFOUT” signal.
4-6-2 TRANSMITTER CIRCUIT
The analog AF signals “AMODIN” from the connected transceiver via the J301 (pin 4) are amplified at the buffer amplifier (IC251, pin 6). The amplified signals are applied to the
linear CODEC IC (IC50, pin 5) to convert 32 bits digital voice
data at the A/D converter section via the “ADIN” line. The
digital signals are applied to the AMBE voice CODEC IC
(IC151) to process code compression, and are then applied
to the CPU (IC204). The digital signals from the CPU convert to the GMSK base band signal at the GMSK modem
(IC252), and are then amplified at the buffer amplifier
(IC253, pin 5). The amplified signals are applied to the connected transceiver via the J301 (pin 3).
4-6-3 RESET CIRCUIT
The UT-115 has the reset IC (IC203). The IC outputs reset
signal to the CPU (IC204, pin 7) when “VDD” port (pin 2)
becomes more than 2.8 V.
4-6-4 RS-232C CIRCUIT
IC351 is a RS-232C compatible serial interface IC which
converts data between the CPU and the external equipment
(EX: Personal Computer).
4-6-5 LEVEL CONVERTER CIRCUIT
The level converter circuit (Q305 and Q306) converts communication data level between the CPU (IC204) and the
connected transceiver’s CPU.
Q301, Q302 and Q303 convert control signals level between
the UT-115 and the connected transceiver.
4-7 UT-115 POWER SUPPLY CIRCUITS
VOLTAGE LINES
4-8 UT-115 PORT ALLOCATIONS
4-8-1 MODEM IC (IC252)
4 - 7
Description
The 5 V voltage from the connected transceiver
via the J301 (pin 29). The 5V line is controlled by
the +5V control circuit (Q50 and Q51). The circuit is controlled by the “PSAVE” signal from the
CPU (IC204, pin 58 and 59).
Common 3.3 V converted from the 5V line by the
3.3V regulator circuit (IC1). One of the 3.3 V line
is controlled by the +3V control circuit (Q400 and
Q401). The circuit is controlled by the “PSAVE”
signal from the CPU (IC204, pin 58 and 59).
Common 3.2 V converted from the 4.5–8 V line
by the 3.2V regulator circuit (IC2). The circuit is
controlled by the “APWR” signal from the CPU
(IC204, pin 16).
Line
5V
3.3V
3.2V
Pin
number
2
7
19
20
21
22
Port
name
MCLK
ACQ
TXDT
RXDT
RXCK
TXCK
Description
Outputs 2.4576 MHz clock signal to
the CPU (IC151, pin 39).
Outputs the PLL band width control
signal while receiving.
Outputs transmitting data signal to the
CPU (IC204, pin 54).
Input port for receiving data signal
from the CPU (IC204, pin 53).
Input port for receive clock signal from
the CPU (IC204, pin 52).
Outputs transmit clock signal to the
CPU (IC204, pin 51).
Linear
CODEC
Buffer
IC253B
Buffer
IC251A
Buffer
IC251B
IC50
IC151
Q305, Q306
IC351
-"232C_RX" signal
to the J301, pin 25
-"232C_TX" signal
to the J301, pin 26
-"TXD_2" signal to
the J301, pin 16
-"RXD_2" signal to
the J301, pin 17
"DAFOUT" signal to
the J301, pin 22
"DMOD" signal
to the J301, pin 3
"FMDET" signal
from the J301, pin 23
"AMODIN" signal
from the J301, pin 4
IC204 IC252
DSP
CODEC
CPU
CODEC
Modem
RS-232C
Level
converter
• UT-115 BLOCK DIAGRAM
4 - 8
Pin
number
7
10
11
16
29
31
33
34
36
37
38
58
59
61
62
Port
name
RES
OSC2
OSC1
APWR
RMUTE_C
PTTOUT_C
ATXD
ACLK
ASTB
ARXD
ARES
PSAVE
BUSY
PTTIN
Description
Input port for the reset signal from the
reset IC (IC203, pin 1).
Low :The CPU is reset.
Outputs 9.8304 MHz reference signal.
Input port for 9.8304 MHz reference
signal.
Outputs 3.2V regulator circuit (IC2,
pin 3) control signal.
Outputs receive AF mute control signal
to the connected transceiver via the
J301 (pin 24).
High :While muting.
Outputs PTT signal to the connected
transceiver via the J301 (pin 2).
High :While transmitting.
Outputs transmit data signal to the
CPU (IC151, pin 32).
Outputs clock signal to the CPU
(IC151, pins 28 and 34).
Outputs strobe signal to the CPU
(IC151, pins 30 and 38).
Input port for receive data signal from
the CPU (IC151, pin 42).
Outputs reset signal to the linear
CODEC IC (IC50, pin 13).
Output power save control signal to
the +3V controller circuit (Q400 and
Q401).
Low :Power save is ON.
Input port for the BUSY signal from the
connected transceiver via the J301
(pin 6).
High :While receiving signals.
Input port for the PTT signal from the
connected transceiver via the J301
(pin 1).
High :While transmitting.
4-8-2 CPU (IC2)
5 - 1
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION
Enter the adjustment mode when adjusting the IC-2200H Then the JIG cable as shown the page 5-2 is required .
■ REQUIRED TEST EQUIPMENT
DC power supply
RF power meter
(terminated type)
Frequency counter
Standard signal
generator (SSG)
FM deviation meter
Oscilloscope
Audio generator
Attenuator
EQUIPMENT GREDE AND RANGE EQUIPMENT GREDE AND RENGE
Output voltage : 13.8 V DC
Current capacity : 20 A or more
Measuring range : 0.1–100 W
Frequency range : 50–400 MHz
Impedance : 50 Ω
SWR : Less than 1.2 : 1
Frequency range : 0.1–400 MHz
Frequency accuracy : ±1 ppm or better
Sensitivity : 100 mV or better
Frequency range : 0.1–400 MHz
Output level : 0.1 µV–32 mV
(–127 to –17 dBm)
Frequency range : 0–400 MHz
Measuring range : 0 to ±5 kHz
Frequency range : DC–400 MHz
Measuring range : 0.01–10 V
Frequency range : 300–3000 Hz
Measuring range : 1–500 mV
Power attenuation : 50 or 60 dB
Capacity : 150 W or more
■ ENTERING THE ADJUSTMENT MODE
q Turn the transceiver’s power OFF.
w Connect the JIG cable to the [MIC] jack.
e Push and hold the [SET] and [MONI] keys, and then turn power ON.
NOTE: Exiting from the adjustment mode when the transciever’s power is OFF.
■ OPERATING ON THE ADJUSTMENT MODE
• Change the adjustment value : [DIAL]
• Verifying the adjustment value : [M/CALL] key
• Forward the adjustment item : [BANK] key
• Go back the adjustment item : [V/MHz] key
• Store the adjustment value in the memory : [S.MW] key
CAUTION: Need to push the [S.MW] key when storing the adjustment value in the memory. Otherwise, the transceiver is not
adjusted properly.
IMPORTANT!: The transceiver need to be cancelled adjustment mode (as following method) to use normal mode when
adjustments are finished, otherwise the transceiver does not work properly.
q: Turn the power OFF.
w: Push and hold [S.MW] and [SET] keys, and then turn the power ON.
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