ICmic X76F400 User Manual
BLOCK DIAGRAM
4K
X76F400
512 x 8 bit
FEATURES
•64-bit password security
—
Read password
•Programmable passwords
—
Allow
s 8 tries before clearing of the array
•1MHz clock rate •2
-
wire
—
2.5 to 5.5V operation
•High
reliability endurance:
•Data retention: 100 years
—8-
lead, SOIC,TSSOP
DESCRIPTION
bit
write operations of the memory array.
dard
TM
This X76F400 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
Secure SerialFlash
The X76F400 is a password access security supervisor,
•One array (496 bytes) two passwords (16 bytes)
—Write password
•Retry counter register
•32-bit response to reset (RST input)
•8 byte sector write mode
serial interface •Low
power CMOS
—Standby current less than 1µA
—Active current less than 3 mA
—100,000 write cycles
•Available in:
containing one 3968-bit Secure Serial Flash array.
Access to the memory array can be controlled by two 64passwords. These passwords protect read and
The X76F400 features a serial interface and software
protocol allowing operation on a popular 2-wire bus.
The bus signals are a clock input (SCL) and a bi-directional
data input and output (SDA).
The X76F400 also features a synchronous response to
reset, providing an automatic output of a hard-wired
32-bit data stream, thereby meeting the industry stan
for memory cards.
The X76F400 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
ICmic
IC MICROSYSTEMS
™
SCL
SDA
Interface
Logic
RST
REV 1.0 7/5/00
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
ISO Reset
Response Register
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Retry Counter
Erase Logic
496 Byte
EEPROM Array
Characteristics subject to change without notice. 1 of 14
X76F400
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
ing a
Reset (RST)
X76F400 will output 32 bits of fixed data, which
DEVICE OPERATION
byte
word
If the X76F400 is in a nonvolatile write cycle a “no ACK”
response to loading of the command byte. If a stop is issued
ated; the part will then reset and
PIN NAMES
PIN CONFIGURATION
After each transaction is completed, the X76F400 will
Symbol
Description
V
V
SOIC
TSSOP
SDA is an open drain serial data input/output pin. Dur
read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
RST is a device reset pin. When RST is pulsed high, the
conforms to the standard for “synchronous responseto-reset.” The part must not be in a write cycle for the
response-to-reset to occur. See Figure 7. If power is
interrupted during the response-to-reset, the response-
to-reset will be aborted and the part will return to the
standby state. The response to reset is “mask
programmable” only!
(SDA = High) response will be issued in
prior to the nonvolatile write cycle, the write
operation will be termin
enter into a standby mode.
(The basic sequence is illustrated in Figure 1.)
SDA
SCL
RST
CC
SS
NC
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
The X76F400 memory array consists of 62 8-byte sectors.
Read or write access to the array always begins at
the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8 bytes.
There are two primary modes of operation for the
X76F400; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8passwords.
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0.’
The user must perform ACK polling to determine the
validity of the password, prior to starting a data transfer
(see Acknowledge Polling). Only after the correct pass
is accepted, and an ACK polling has been
performed, can the data transfer occur. See Figure 1.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “response-to-reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
VSS
NC
SDA
NC
VCC
NC
NC
VSS
1
2
3
4
1
2
3
4
VCC
8
RST
7
SCL
6
NC
5
RST
8
SCL
7
SDA
6
NC
5
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
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Characteristics subject to change without notice. 2 of 14
X76F400
Figure 1. X76F400 Device Operation
Retry Counter
before any action is taken. The counter will increment with
Device Protocol
is a master and the device being controlled is the slave.
tions.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
Start Condition
eded by the start condition, which
continuously monitors the SDA and
A start may be issued t
start cannot be generated while the part is outputting data.
Stop Condition
All communicatio
of SDA when SCL is HIGH. The stop condition is also used
Acknowledge
lease the bus after transmitting 8 bits.
Load Command/Address Byte
Figure 2. Data Validity
Load 8-Byte
Password
Verify Password
Acceptance by
Use of ACK Polling
Read/Write
Data Bytes
LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 2 and 3.
All commands are prec
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F400
SCL lines for the start condition, and will not
respond to any command until this condition is met.
o terminate the input of a control
byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or write
command. Because of the push/pull output, a
The X76F400 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of the
passwords are cleared to “0.” If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
The X76F400 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
The master will always initiate data transfers and
provide the clock for both transmit and receive opera
Therefore, the X76F400 will be considered a
slave in all applications.
Starts are inhibited while a write is in progress.
ns must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
to reset the device during a command or data
input sequence, leaving the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will re
During the ninth clock cycle the receiver will pull
the SDA line LOW to acknowledge that it received the 8
bits of data.
The X76F400 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F400 will respond with an acknowl-
edge after the receipt of each subsequent 8-bit word.
SCL
SDA
Data Stable Data
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Change
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Characteristics subject to change without notice. 3 of 14
X76F400
Figure 3. Definition of Start and
Stop Conditions
Table 1. X76F400 Instruction Set
Command After Start
Command Description
Password Used
SCL
Illegal command codes will be disregarded. The part will
tions
PROGRAM OPERATIONS
Sector Write
written. Data is written starting at the first address of a
tion is
more or less than 8 bytes are transferred, the data in the
ACK Polling
tage of
dition
with the nonvolatile write operation, it will issue a “no
completed, an “ACK” will be returned and the host can then
Data ACK Polli
ng Sequence
SDA
START Condition STOP Condition
1 S
S
S
S
S
S
0
1
0
S
S
1
1
0
1 S
5
4
3
2
S
S
5
S
4
3
2
1 1 1 1 1 1 0 0 Change Write Password Write
1 1 1 1 1 1 1 0 Change Read Password Write
0 1 0 1 0 1 0 1 Password ACK Command None
respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera
require a password.
Sector Write Write
Sector Read Read
-
ACK” in response. If the nonvolatile write operation is
proceed with the rest of the protocol.
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be
sector and 8 bytes must be transferred. After the last
byte to be transferred is acknowledged, a stop condi
issued which starts the nonvolatile write cycle. If
sector remains unchanged.
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F400 initiates the
internal nonvolatile write cycle. In order to take advan
the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con
followed by the new command code of 8 bits
(first byte of the protocol). If the X76F400 is still busy
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Write Sequence
Completed Enter ACK
Polling
Issue START
Issue New
Command Code
ACK
Returned?
YES
PROCEED
Characteristics subject to change without notice. 4 of 14
NO
X76F400
After the password sequence, there is always a nonvola-
tile
write cycle. This is done to discourage random
guesses of the password if the device is being tampered with.
with regular acknowledge polling the user can either time
rect, the nonvolatile cycle
Password ACK Polling Sequence
READ OPERATIONS
write operations but with a different command code.
Sect
or Read
With sector read, a sector address is supplied with the read
continue to be read out. After the last bit has been read,
ACK Command
In order to continue the transaction, the X76F400
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
Read operations are initiated in the same manner as
out for 10ms and then issue the ACK polling once,
or continuously loop as described in the flow.
If the password inserted is cor
in response to the password ACK polling
sequence is over, and an “ACK” is returned.
If the password inserted is incorrect, a “no ACK” is
returned, even if the nonvolatile cycle is over. There-
fore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.
Password Load
Completed Enter ACK
Polling
Issue START
Issue Password
command. Once the password has been
acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A
read operation always begins at the first byte in the
sector, but may stop at any time. Random accesses to
the array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is automatically set to the first sector in the array and data can
a stop condition is generated without sending a
preceding acknowledge.
ACK
Returned?
YES
PROCEED
REV 1.0 7/5/00
NO
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Characteristics subject to change without notice. 5 of 14
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